參數(shù)資料
型號: 73S1209F-68IM/F
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: POWER SUPPLY MANAGEMENT CKT, QCC68
封裝: LEAD FREE, QFN-68
文件頁數(shù): 98/123頁
文件大?。?/td> 1385K
代理商: 73S1209F-68IM/F
73S1209F Data Sheet
DS_1209F_004
VCC
VCCOK
RSTCRD
RST
CLK
IO
t1
t2
t3
t4
tto
VCCSEL
bits
t1: The time from setting VCCSEL bits until VCCOK = 1.
tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),
activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when
sequence is starting.
t2: time from start of activation (no external indication) until IO goes into reception mode (= 1).
This is
approximately 4 SCCLK (or SCECLK) clock cycles.
t3: minimum one half of ETU period.
t4: ETU period.
Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK,
either from the card or from the 73S1209F. The RST signal to the card is directly controlled by the RSTCRD bit
(non-inverted) via the MPU and is shown as an example of a possible RST pattern.
Figure 19: Synchronous Activation
IO reception on
RST
CLK
CLKOFF
CLKLVL
Rlength Interrupt
RLength Count
RLenght = 1
TX/RXB Mode bit
(TX = '1')
1. Clear CLKOFF after Card is in reception mode.
2. Set RST bit.
3. Interrupt is generated when Rlength counter is MAX.
4. Read and clear Interrupt.
5. Clear RST bit.
6. Toggle TX/RXB to reset bit counter.
7. Reload RLength Counter.
Count MAX
1
2
4
7
5
t1. CLK wll start at least 1/2 ETU after CLKOFF is set low
when CLKLVL = 0
t1
3
6
Figure 20: Example of Sync Mode Operation: Generating/Reading ATR Signals
76
Rev. 1.2
相關(guān)PDF資料
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73S1209F-44IMR/F POWER SUPPLY MANAGEMENT CKT, QCC44
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