參數(shù)資料
型號: 73S1210F-44IM/F/P
廠商: Maxim Integrated Products
文件頁數(shù): 102/126頁
文件大?。?/td> 0K
描述: IC SMART CARD READER PROG 44-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART
外圍設備: LED,POR,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 管件
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
77
VCC
VCCOK
RSTCRD
RST
CLK
IO
t1
t2
t3
t4
tto
VCCSEL
bits
t1: The time from setting VCCSEL bits until VCCOK = 1.
tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),
activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when
sequence is starting.
t2: time from start of activation (no external indication) until IO goes into reception mode (= 1). This is approximately
4 SCCLK (or SCECLK) clock cycles.
t3: minimum one half of ETU period.
t4: ETU period.
Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK,
either from the card or from the 73S1210F. The RST signal to the card is directly controlled by the RSTCRD bit
(non-inverted) via the MPU and is shown as an example of a possible RST pattern.
Figure 20: Synchronous Activation
IO reception on
RST
CLK
CLKOFF
CLKLVL
Rlength Interrupt
RLength Count
RLenght = 1
TX/RXB Mode bit
(TX = '1')
1. Clear CLKOFF after Card is in reception mode.
2. Set RST bit.
3. Interrupt is generated when Rlength counter is MAX.
4. Read and clear Interrupt.
5. Clear RST bit.
6. Toggle TX/RXB to reset bit counter.
7. Reload RLength Counter.
Count MAX
1
2
4
7
5
t1. CLK wll start at least 1/2 ETU after CLKOFF is set low
when CLKLVL = 0
t1
3
6
Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals
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