參數(shù)資料
型號(hào): 73S1210F-44IM/F/P
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 98/126頁(yè)
文件大?。?/td> 0K
描述: IC SMART CARD READER PROG 44-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART
外圍設(shè)備: LED,POR,WDT
輸入/輸出數(shù): 8
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤(pán)
包裝: 管件
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DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
73
Figure 16: Asynchronous Activation Sequence Timing
VCC
IO
RST
CLK
t1
t2
t3
t4
t5
Firmware sets
VCCSEL to 00
CMDVCCnB
t5 delay or
Card Event
t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0
(see t5, VCCOff_tmr) occurs until RST is asserted low.
t2: Time after RST goes low until CLK stops.
t3: Time after CLK stops until IO goes low.
t4: Time after IO goes low until VCC is powered down.
t5: Delayed VCC off time (in ETUs per VCCOff_tmr bits). Only in effect due to firmware
deactivation.
Figure 17: Deactivation Sequence
1.7.15.3
Data Reception/Transmission
When a 12Mhz crystal is used, the smart card UART will generate a 3.69Mhz (default) clock to both
smart card interfaces. This will allow approximately 9600bps (1/ETU) communication during ATR (ISO
7816 default). As part of the PPS negotiation between the smart card and the reader, the firmware may
determine that the smart card parameters F & D may be changed. After this negotiation, the firmware
may change the ETU by writing to the SFR FDReg to adjust the ETU and CLK. The firmware may also
change the smart card clock frequency by writing to the SFR SCCLK (SCECLK for external interface).
Independent clock frequency control is provided to each smart card interface. Clock stop high or Clock
stop low is supported in asynchronous mode. Figure 18 shows the ETU and CLK control circuits. The
firmware determines when clock stop is supported by the smart card and when it is appropriate to go into
that mode (and when to come out of it). The smart card UART is clocked by the same clock that is
provided to the selected smart card. The transition between smart card clocks is handled in hardware to
eliminate any glitches for the UART during switchover. The external smart card clock is not affected
when switching the UART to communicate with the internal smart card.
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