參數(shù)資料
型號： 73S1210F-68IMR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
封裝： LEAD FREE, QFN-68
文件頁數(shù)： 59/126頁
文件大小： 1231K
代理商： 73S1210F-68IMR/F
73S1210F Data Sheet
DS_1210F_001
38
Rev. 1.4
Table 26: Control Bits for External Interrupts
Enable Bit
Description
Flag Bit
Description
EX0
Enable external interrupt 0
IE0
External interrupt 0 flag
EX1
Enable external interrupt 1
IE1
External interrupt 1 flag
EX2
Enable external interrupt 2
IEX2
External interrupt 2 flag
EX3
Enable external interrupt 3
IEX3
External interrupt 3 flag
EX4
Enable external interrupt 4
IEX4
External interrupt 4 flag
EX5
Enable external interrupt 5
IEX5
External interrupt 5 flag
EX6
Enable external interrupt 6
IEX6
External interrupt 6 flag
1.7.5.4
Power Down Interrupt Logic
The 73S1210F contains special interrupt logic to allow INT0 to wake up the CPU from a power down
(CPU STOP) state. See the Power Control Modes section for details.
1.7.5.5
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 27.
Table 27: Priority Level Groups
Group
0
External interrupt 0
Serial channel 1 interrupt
1
Timer 0 interrupt
–
External interrupt 2
2
External interrupt 1
–
External interrupt 3
3
Timer 1 interrupt
–
External interrupt 4
4
Serial channel 0 interrupt
–
External interrupt 5
5
–
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or
clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level
are received simultaneously, an internal polling sequence as per Table 31 determines which request is
serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler.
Interrupt Priority 0 Register (IP0): 0xA9
0x00
Table 28: The IP0 Register
MSB
LSB
–
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Note: WDTS is not used for interrupt controls.
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