參數(shù)資料
型號(hào): 73S8023C-DB
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 9/27頁(yè)
文件大小: 0K
描述: BOARD DEMO 73S8023C 32-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
73S8023C Data Sheet
DS_8023C_019
Rev. 1.5
17
11 Typical Application Schematic
32QFN
73S8023C
1
4
3
8
6
7
12
13
14
15
24
23
GND
NC
VDD
PRES
GND
CLK
RST
VCC
XTALOUT
XTALIN
2
LIN
5 PWRDN
CS
16
CLKSEL
29
30
31
28
27
26
CLKDIV
1
CLKDIV
2
5
V
/3
V
AUX
2
UC
AUX
1
UC
I/
OUC
25
STROBE
32
CLKOUT
17
18
19
20
21
22
VDDF_ADJ
CMDVCC
RSTIN
VDD
GND
OFF
10
9
11
AUX
2
I/
O
AUX
1
See NOTE 4
VDD
PWRDN_from_uC
Y1
CRYSTAL
C2
22pF
C1
SO7816=1uF,
NDS/EMV=3.3uF
See NOTE 5
RSTIN_from_uC
CLKDIV2_from_uC
CLK track should be routed
far from RST, I/O, C4 and
C8.
I/OUC_to/from_uC
R1
Rext1
See NOTE 1
VDD
C9
100nF
External_clock_from uC
C4
100nF
C3
22pF
AUX1UC_to.from_uC
See NOTE 6
C5
10uF
AUX2UC_to/from_uC
See NOTE 3
See NOTE 1
CLKOUT_to_uC
VDD
CLKDIV1_from_uC
CMDVCC_from_uC
5V/3V_select_from_uC
OFF_interrupt_to_uC
R3
Rext2
- OR -
See note 7
Smart Card Connector
1
2
3
4
5
6
7
8
9
VCC
RST
CLK
C
4
GND
VPP
I/
O
C
8
SW
-1
SW
-2
VDD
L1
10uH
CS_from_uC
CLKSEL_from_uC
STROBE_from_uC
See note 2
NOTES:
1) VDD supply must be = 2.7V to 3.6V DC).
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Pin can not float. Must be driven or connected to GND if
power down function is not used.
6) Internal pull-up allows it to be left open if unused.
7) Rext1 and Rext2 are external resistors to ground and
VDD to modify the VDD fault voltage. Can be left open.
2) Keep L1 close to pin 2.
VDD
R2
20K
10
Card detection
switch is
normally
closed.
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
C8
C7
C6
27pF
8) Capacitors C7 and C8 are optional. C6 is mandatory for NDS.
Figure 11: 73S8023C – Typical Application Schematic
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