參數(shù)資料
型號： 73S8023C-IMR/F
廠商： Maxim Integrated Products
文件頁數(shù)： 2/27頁
文件大小： 0K
描述： IC SMART CARD INTERFACE 32-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
控制器類型： 智能卡接口
電源電壓： 2.7 V ~ 3.6 V
電流 - 電源： 4.9mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 帶卷 (TR)
73S8023C Data Sheet
DS_8023C_019
10
Rev. 1.5
6
Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8023C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the
CMDVCC signal is driven high from
the host controller).
The host controller invokes the power down state when it is desirable to save power. The signals PRES
and
PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller
must then set PWRDN low and wait for the internal stabilization time prior to starting any card session
(prior to turning
CMDVCC low).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators and
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present,
OFF can be used as an indication that the circuit has completed its
recovery from power-down state.
OFF will go high at the end of the stabilization period. Should
CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be
taken into account and the card interface will remain inactive. Since
CMDVCC is taken into account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.
Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
Figure 2: Power Down Mode Operation: CS = high
7
Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
PRES
OFF
PWRDN
Internal RC OSC
CMDVCC
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
CMDVCC=0
EMV / ISO deactivation
time ~= 100 uS
~10ms
PWRDN has effect when
the cardi s deactivated
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