Command V
參數(shù)資料
型號: 73S8024C-DB
廠商: Maxim Integrated Products
文件頁數(shù): 18/22頁
文件大小: 0K
描述: BOARD DEMO 73S8024C 28-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
DS_8024C_023
73S8024C Data Sheet
Rev. 1.3
5
1.4
Microcontroller Interface
Name
Pin
(SO)
Description
CMDVCC
19
Command VCC (negative assertion): Logic low on this pin causes the DC-DC
converter to ramp the VCC supply to the card and initiates a card activation sequence.
5V/
#V
3
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic
low selects 3 volt operation. When the part is to be used with a single card voltage,
this pin should be tied to either GND or VDD. However, it includes a high impedance
pull-up resistor to default this pin high (selection of 5 V card) when unconnected.
PWRDN
8
Power Down control input (active high): When Power Down (PD) mode is
activated; all internal analog functions are disabled to place the 73S8024C in its
lowest power consumption mode. The PD mode is allowed only out of a card
session (= PWRDN high is not taken into account when CMDVCC = 0). Must be
tied to ground when the power down function is not used.
CLKDIV1
CLKDIV2
1
2
Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card
clock. These pins include pull-down resistors.
CLKDIV1
CLKDIV2
Clock Rate
0
XTALIN/8
0
1
XTALIN/4
1
XTALIN/2
1
0
XTALIN
OFF
23
Interrupt signal to the processor (active low): Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20
kΩ pull-up to V
DD.
RSTIN
20
Reset Input: This signal is the reset command to the card.
I/OUC
26
System controller data I/O to/from the card. Includes internal pull-up resistor to VDD.
AUX1UC
27
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to VDD.
AUX2UC
28
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to VDD.
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