參數(shù)資料
型號: 73S8024C-DB
廠商: Maxim Integrated Products
文件頁數(shù): 4/22頁
文件大小: 0K
描述: BOARD DEMO 73S8024C 28-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
73S8024C Data Sheet
DS_8024C_023
12
Rev. 1.3
11 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power on reset and they are in the high state
when the activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for
more details on when the I/O reception is on.
The state of the I/OUC, AUX1UC, and AUX2UC is high after power on reset. Within a card session and
when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the input
I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both
I/O lines return to their neutral state.
Figure 7 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals is shown in Figure 8.
Neutral
State
I/OUC
in
I/O
reception
I/OICC
in
No
Yes
No
Yes
No
Yes
I/O
&
not I/OUC
I/OUC
&
not I/O
I/OUC
I/O
yes
Figure 7: I/O and I/OUC State Diagram
Figure 8: I/O – I/OUC Delays: Timing Diagram
Delay from I/O to I/OUC:
tIO_HL = 100 ns
tIO_LH = 25 ns
Delay from I/OUC to I/O:
tI/OUC_HL = 100 ns
tI/OUC_LH = 25 ns
IO
IOUC
tIO_HL
tIO_LH
tIOUC_HL
tIOUC_LH
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