參數(shù)資料
型號(hào): 73S8024C-ILR/F
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/22頁(yè)
文件大?。?/td> 0K
描述: IC SMART CARD INTERFACE 28-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,500
控制器類(lèi)型: 智能卡接口
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 帶卷 (TR)
DS_8024C_023
73S8024C Data Sheet
Rev. 1.3
11
Figure 5: Deactivation Sequence
10
OFF and Fault Detection
There are two cases for which the system controller can monitor the
OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.
Monitoring Outside a Card Session
In this condition,
CMDVCC is always high, OFF is low if the card is not present, and high if the card is
present. Because it is outside a card session, any fault detection will not act upon the
OFF signal. No
deactivation is required during this time.
Monitoring During a Card Session
CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same
time that
OFF is set low, the sequencer starts the deactivation process.
Figure 6 shows the timing diagram for the
CMDVCC, PRES, and OFF signals during a card session and
outside the card session.
PRES
OFF
CMDVCC
VCC
outside card session
within card session
OFF is low by
card extracted
OFF is low by
any fault
within card
session
Figure 6: Timing Diagram – Management of the Interrupt Line
OFF
t1
≥ 0.5 s, timing by 1.5 MHz internal Oscillator
t2
≥ 7.5 s
t3
≥ 0.5 s
t4
≥ 0.5 s
t5 = depends on VCC filter capacitor
For NDS application, CF = 1 F making t1 + t2 + t3 + t4 + t5 < 100 s
RST
CLK
I/O
VCC
t1
t2
t3
t4
t5
CMDVCC
-- OR --
OFF
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