參數(shù)資料
型號(hào): 74ABT3284
廠商: National Semiconductor Corporation
英文描述: 18-Bit Synchronous Datapath Multiplexer
中文描述: 18位同步數(shù)據(jù)通道多路復(fù)用器
文件頁(yè)數(shù): 2/12頁(yè)
文件大?。?/td> 170K
代理商: 74ABT3284
Functional Description
The 74ABT3284 is a bi-directional registered data-path rout-
ing device which can multiplex/de-multiplex four 9-bit ‘‘A-
side’’ data ports (Ports A, B, C, D) onto/from one 9-bit ‘‘X-
side’’ port (Port X). Alternatively, it can be configured for
mux/demux of two 18-bit data paths (Ports A and C, B and
D) onto/from one 18-bit data path (Ports X and Y).
Each of the six 9-bit I/O ports have independent active low
TRI-STATE
é
output enable control logic which can be con-
figured to operate asynchronously or synchronously. With
MODEDSO low, direct asynchronous output control is pro-
vided. With MODEDSO high, output enable control is as-
serted synchronously on the positive edge of the CPDIN
clock. All I/O port inputs are continuously active allowing
output state feedback.
The four A-side ports (A, B, C, D) contain independently
enabled input and output data registers for storage of data
passing in either direction. The input register (AIR, BIR, CIR,
DIR) is loaded/held on the positive edge of CPDAX when
the respective Load Control pin (LDAI, LDBI, LDCI, LDDI) is
asserted high/low. The Input Registers can be loaded with
data from the corresponding A-side port. The output register
(AOR, BOR, COR, DOR) is loaded/held on the positive
edge of CPDXA when the respective Load Control pin
(LDAO, LDBO, LDCO, LDDO) is asserted high/low. The
Output Registers can be loaded with data from Port X when
MODEDWS is asserted low. When MODEDWS is asserted
high, the Output Registers A and C can be loaded with Port
X data and the B and D Output Registers can be loaded with
data from Port Y.
When routing data from A-side to X-side, Data Path Control
is provided for the following options via the SA2X inputs;
Transparent mode where Input Register is bypassed but
can simultaneously monitor A-side data; Registered Mode
where X-side receives data from the selected Input Regis-
ters; Readback Mode where X-side receives data from the
selected Output Registers. A-side data from Ports A, B, C,
or D can be selected to Port X via the XSEL data path select
inputs. Ports B or D can be selected to Port Y via the YSEL
data path select input.
When routing data from X-side to A-side, Data Path Control
is provided for the following options via the ASEL inputs;
Transparent mode where Output Register is bypassed but
can simultaneously monitor X-side data; Registered Mode
where the A-side Port receives data from the corresponding
Output Register; Readback Mode where the A-side Port re-
ceives data from the corresponding Input Registers.
MODEDWS asserted low selects Port X data to be passed
to Ports A, B, C, and D. With MODEDWS asserted high,
Port X data is passed to Ports A and C with Port Y data
passed to Ports B and D.
All Data Path Control Inputs and Input/Output Register
Load Enable Inputs are active high and can be asserted
asynchronously or synchronously. When MODEDSC is low,
these inputs operate asynchronously. When MODEDSC is
high, the inputs are asserted synchronously on the positive
edge of the CPDIN clock.
When operating the Data Path Control and/or the Output
Enable Input groups with MODEDSC and/or MODEDSO
‘‘hard wired’’ high for synchronous mode, a single pre-clock
of CPDIN will be required following power-up to insure that
all internal synchronous control registers are in the appropri-
ate known state. if the application requires ‘‘on the fly’’’
changes from asynchronous to synchronous operation,
then the respective control/enable pin data must be pre-
clocked via CPDIN and held steady prior to and during any
low to high transition of the MODEDSO or MODEDSC to
properly initiate the sync control registers for synchronous
control mode.
Pin Descriptions
Pin Name
Description
Operation
OEa
Output Enable Inputs
(Active Low)
Sync/Async
LDaI
Load Enable Inputs for the
Input Registers
Sync/Async
LDaO
Load Enable Inputs for the
Output Registers
Sync/Async
ASEL(0,1)
A-Side Data Path Select Inputs
Sync/Async
SA2X(0,1)
X-Side Data Path Select Inputs
Sync/Async
XSEL(0,1)
X-Port Data Path Select Inputs
Sync/Async
YSEL
Y-Port Data Path Select Input
Sync/Async
MODEDW
Word Mode Select Input for
the X/Y to A-Side Direction
Sync/Async
MODEDSO Enable Input for Synchronous
Output Enable Control
Async
MODEDSC Enable Input for Synchronous
Data Path Control
Async
CPDIN
Clock Input for Synchronous
Control (Positive Edge Trigger)
CPDAX
Clock Input for Input Registers
(Positive Edge Trigger)
CPDXA
Clock Input for Output Registers
(Positive Edge Trigger)
2
相關(guān)PDF資料
PDF描述
74ABT3284VJG 18-Bit Synchronous Datapath Multiplexer
74AC00 QUAD 2-INPUT NAND GATE
74AC00B QUAD 2-INPUT NAND GATE
74AC00M QUAD 2-INPUT NAND GATE
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參數(shù)描述
74ABT3284VJG 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:18-Bit Synchronous Datapath Multiplexer
74ABT32D 功能描述:邏輯門(mén) QUAD 2-INPUT OR GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
74ABT32D,112 功能描述:邏輯門(mén) QUAD 2-INPUT OR GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
74ABT32D,118 功能描述:邏輯門(mén) QUAD 2-INPUT OR GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
74ABT32DB 功能描述:邏輯門(mén) QUAD 2-INPUT OR GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量(輸入/輸出):2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel