參數(shù)資料
型號: 74ABT3284
廠商: National Semiconductor Corporation
英文描述: 18-Bit Synchronous Datapath Multiplexer
中文描述: 18位同步數(shù)據(jù)通道多路復用器
文件頁數(shù): 3/12頁
文件大小: 170K
代理商: 74ABT3284
Function Tables
Output Enable Control Table
Inputs
Outputs
Control
Mode
Function
OE (A, B, C, D, X, Y)
MODEDSO
CPDIN
Port
A, B, C, D, X, Y
L
L
X
ENABLE
ASYNC
ENABLED OUTPUT, I/O input always active
H
L
X
DISABLE
ASYNC
DISABLED OUTPUT, I/O input always active
(Notes 2, 3)
H (Note 1)
L
(Note 3)
SYNC
(Note 3)
Note 1:
Low to High transitions of MODEDSO must be immediately preceeded by a low to high transition (clock edge) on CPDIN while holding Synchronous
Control Inputs OE (A, B, C, D, X, Y) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to
synchronous.
Note 2:
OE (A, B, C, D, X, Y) levels are synchronously asserted by the positive transition of CPDIN when MODEDSO is high.
Note 3:
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CPDIN.
A Side Data Path Select Function Table
Inputs
Data Path
Control
Mode
Function
ASEL(1)
ASEL(0)
MODEDSC
CPDIN
From
Reg/Port
To
Port
L
L
L
X
(A, B, C, D) IR
A, B, C, D
ASYNC
Readback; Contents of Input Register
(A, B, C, D) IR to Port (A, B, C, D)
L
H
L
X
(A, B, C, D) OR
A, B, C, D
ASYNC
Clocked Path; Contents of Output
Register (A, B, C, D) OR to Port (A, B,
C, D)
H
L
L
X
Port X
A, B, C, & D
ASYNC
Transparent Path; Port X to Port A, B,
C, & D
H
H
L
X
Port X
A & C
ASYNC
Transparent Path; Port X to Port A &
C
Transparent Path; Port Y to Port B &
D
Port Y
B & D
(Notes 2, 3)
(Notes 2, 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1:
Low to High transitions of MODEDSC must be immediately preceeded by a low to high transition (clock edge) on CPDIN while holding Synchronous
Control Inputs ASEL(0) and ASEL(1) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to
synchronous.
Note 2:
ASEL(0) and ASEL(1) levels are synchronously asserted by the positive transition of CPDIN when MODEDSC is high.
Note 3:
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CPDIN.
Input Register Control Table
Inputs
Register
Control
Mode
Function
Port
LD(A, B, C, D) I
MODEDSC
CPDIN
CPDXA
(A, B, C, D) IR
(A, B, C, D)
X
L
L
X
L
HOLD
ASYNC
HOLD; Input Register holds previous
state.
L (H)
H
L
X
L
L (H)
ASYNC
LOAD; Port A, B, C, D clocked to Input
Register (A, B, C, D) IR via CPDAX
positive edge
(Note 3)
(Notes 2, 3)
H (Note 1)
L
(Note 3)
(Note 3)
SYNC
(Note 3)
Note 1:
Low to High transitions of MODEDSO must be immediately preceeded by a low to high transition (clock edge) on CPDIN while holding Synchronous
Control Inputs LDAI, LDBI, LDCI, and LDDI steady to preset internal registers and assure predictable operation during the control mode change from asynchronous
to synchronous.
Note 2:
LDAI, LDBI, LDCI and LDDI levels are synchronously asserted by the positive transition of CPDIN when MODEDSC is high.
Note 3:
Synchronous Control Mode Functions are same as Asynchronous at time T
a
1 of CPDIN.
3
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74ABT3284VJG 制造商:NSC 制造商全稱:National Semiconductor 功能描述:18-Bit Synchronous Datapath Multiplexer
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