參數(shù)資料
型號(hào): 74ACT74SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual D-Type Positive Edge-Triggered Flip-Flop
中文描述: ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14
文件頁數(shù): 5/11頁
文件大小: 95K
代理商: 74ACT74SJ
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note 1)
1) C
PD
isdefined as the value ofthe IC’s internalequivalent capacitance which iscalculated fromtheoperating currentconsumption without load. (Refer to
Test Circuit).Average operating current can beobtained by the followingequation.I
CC
(opr) =C
PD
V
CC
f
IN
+I
CC
/n (per circuit)
5.0
5.0
4
pF
pF
43
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
, Input t
r
= t
f
=3ns)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
5.0
(*)
T
A
= 25
o
C
Min.
Typ.
-40 to 85
o
C
Min.
Max.
10.0
Max.
11.0
t
PLH
t
PHL
t
PLH
t
PHL
t
w
Propagation Delay Time
CK to Q
Propagation Delay Time
PR or CLR to Q or Q
CK Pulse Width, HIGH
or LOW
Setup Time Q to CK
HIGH or LOW
Hold Time Q to CK
HIGH or LOW
Removal Time PR or
CLR to CK
Maximim Clock
Frequency
(*) Voltagerange is5V
±
0.5V
5.0
ns
5.0
(*)
5.0
10.0
11.0
ns
5.0
(*)
1.5
5.0
6.0
ns
t
s
5.0
(*)
0.5
3.0
3.5
ns
t
h
5.0
(*)
-0.5
1.0
1.0
ns
t
rem
5.0
(*)
-0.7
1.0
1.0
ns
f
MAX
5.0
(*)
100
250
85
MHz
74ACT74
5/11
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PDF描述
74ACT74 8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path 56-BGA MICROSTAR JUNIOR -40 to 85
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