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參數(shù)資料
| 型號： | 74ACT843SCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 9-Bit D-Type Latch |
| 中文描述： | ACT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013, SOIC-24 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 154K |
| 代理商： | 74ACT843SCX |
Functional Description
The ’AC/’ACT843 consists of nine D-type latches with
TRI-STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the data
in transition. On the LE HIGH-to-LOW transition, the data
that meets the setup times is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in the high impedance state. In
addition to the LE and OE pins, the ’AC/’ACT843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal
for parity bus interfacing in high performance systems.
When CLR is LOW, the outputs are LOW if OE is LOW.
When CLR is HIGH, data can be entered into the latch.
When PRE is LOW, the outputs are HIGH if OE is LOW.
Preset overrides CLR.
Function Tables
Inputs
Internal
Outputs
Function
CLR
PRE
OE
LE
D
Q
O
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
L
H
H
L
X
X
X
L
L
L
H
X
L
H
X
X
X
X
X
X
L
H
NC
L
H
NC
H
L
H
L
H
Z
Z
Z
L
H
NC
H
L
H
Z
Z
High Z
High Z
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
NC
e
No Change
Logic Diagram
TL/F/9800–5
2
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| 74ACT86MTR | 功能描述:邏輯門 Quad Exclusive OR RoHS:否 制造商:Texas Instruments 產品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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