參數(shù)資料
型號(hào): 74ALS996
廠商: Texas Instruments, Inc.
英文描述: 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
中文描述: 8位D型邊沿觸發(fā)回讀鎖存
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 133K
代理商: 74ALS996
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR Q OUTPUTS
From Output
Under Test
Test
Point
500
S1
CL
(see Note A)
7 V
500
LOAD CIRCUIT FOR D OUTPUTS
From Output
Under Test
Test
Point
1 k
S1
CL
(see Note A)
7 V
1 k
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V
1.3 V
tPHZ
tPLZ
0.3 V
tPZL
tPZH
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
0 V
VOH
VOL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
tPHL
tPLH
tPLH
tPHL
Input
Out-of-Phase
Output
(see Note B)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
VOL
VOH
VOH
VOL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
Figure 1. Load Circuits and Voltage Waveforms
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