參數(shù)資料
型號： 74ALVCHR16269AVRE4
廠商： Texas Instruments, Inc.
英文描述： 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
中文描述： 12位到24位注冊巴士換熱具有三態(tài)輸出
文件頁數(shù)： 1/12頁
文件大?。?/td> 168K
代理商： 74ALVCHR16269AVRE4
www.ti.com
FEATURES
Member of the Texas Instruments Widebus
Family
Operates From 1.65 V to 3.6 V
Max t
pd
of 5.2 ns at 3.3 V
±
24-mA Output Drive at 3.3 V
All Outputs Have Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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OEA
OEB1
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
NC
SEL
OEB2
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
NC No internal connection
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050O–AUGUST 1995–REVISED SEPTEMBER 2004
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCHR16269A is used in applications in
which two ports must be multiplexed onto, or
demultiplexed from, a single port. It is particularly
suitable
as
an
interface
DRAMs and high-speed microprocessors.
between
synchronous
Data is stored in the internal B-port registers on the
low-to-high transition of the clock (CLK) input, when
the appropriate clock-enable (CLKENA) inputs are
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port. For data transfer in the B-to-A
direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The
register on the A output permits the fastest possible data transfer, thus extending the period during which the
data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK.
Data flow is controlled by the active-low output enables (OEA, OEB1, and OEB2).
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
SN74ALVCHR16269AL
SN74ALVCHR16269ALR
SN74ALVCHR16269AGR
SN74ALVCHR16269AVR
TOP-SIDE MARKING
Tube
Tape and reel
Tape and reel
Tape and reel
SSOP – DL
ALVCHR16269A
-40
°
C to 85
°
C
TSSOP – DGG
TVSOP – DGV
ALVCHR16269A
VR269A
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1995–2004, Texas Instruments Incorporated
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