![](http://datasheet.mmic.net.cn/230000/74F169_datasheet_15562966/74F169_2.png)
Philips Semiconductors
Product specification
74F169
4-bit up/down binary synchronous counter
2
1996 Jan 05
853–0350 16190
FEATURES
Synchronous counting and loading
Up/Down counting
Modulo 16 binary counter
Two Count Enable inputs for n-bit cascading
Positive edge-triggered clock
Built-in carry look-ahead capability
Presettable for programmable operation
DESCRIPTION
The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down
counter featuring an internal carry look-ahead for applications in
high-speed counting designs. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when instructed by the Count
Enable inputs and internal gating. This mode of operation eliminates
the output spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the flip-flops
on the Low-to-High transition of the clock.
The counter is fully programmable; that is, the outputs may be
preset to either level.
Presetting is synchronous with the clock and takes place regardless
of the levels of the Count Enable inputs. A Low level on the Parallel
Enable (PE) input disables the counter and causes the data at the
D
n
input to be loaded into the counter on the next Low-to-High
transition of the clock.
The direction of counting is controlled by the Up/Down (U/D) input; a
High will cause the count to increase, a Low will cause the count to
decrease.
The carry look-ahead circuitry provides for n-bit synchronous
applications without additional gating. Instrumental in accomplishing
this function are two Count Enable inputs (CET
,
CEP) and a
Terminal Count (TC) output. Both Count Enable inputs must be Low
to count. The CET input is fed forward to enable the TC output. The
TC output thus enabled will produce a Low output pulse with a
duration approximately equal to the High level portion of the Q
0
output. The Low level TC pulse is used to enable successive
cascaded stages.
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
CC
TC
Q
0
Q
1
Q
2
Q
3
CET
PE
U/D
CP
D
0
D
1
D
2
D
3
CEP
GND
SF00766
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F169
115MHz
35mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
PKG
DWG #
16-pin plastic DIP
N74F169N
SOT38-4
16-pin plastic SO
N74F169D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D
0
- D
3
CEP
Parallel data inputs
1.0/1.0
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/1.2mA
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
Count Enable parallel input (active Low)
1.0/1.0
CET
Count Enable Trickle input (active Low)
1.0/2.0
CP
Clock input (active rising edge)
1.0/1.0
PE
Parallel Enable input (active Low)
1.0/1.0
U/D
Up/Down count control input
1.0/1.0
Q
0
- Q
3
TC
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20
μ
A in the High state and 0.6mA in the Low state.
Flip-flop outputs
50/33
1.0mA/20mA
Terminal count output (active Low)
50/33
1.0mA/20mA