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參數(shù)資料
| 型號： | 74F173 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad D-type flip-flop 3-State |
| 中文描述： | 四D型觸發(fā)器三態(tài) |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 88K |
| 代理商： | 74F173 |
Philips Semiconductors
Product specification
74F173
Quad D-type flip–flop (3-State)
2
August 31, 1990
853–1160 00286
FEATURES
Edge–triggered D–type register
Gated clock enable for hold ”do nothing” mode
3–state output buffers
Gated output enable control
Speed upgrade of N8T10 and current sink upgrade
Controlled output edges to minimize ground bounces
48mA sinking capability
DESCRIPTION
The 74F173 is a high speed 4–bit parallel load register with
clock enable control, 3–state buffered outputs, and master
reset (MR). When the two clock enable (E0 and E1) inputs
are low, the data on the D inputs is loaded into the register
simultaneously with low–to–high clock (CP) transition. When
one or both enable inputs are high one setup time before the
low–to–high clock transition, the register retains the previous
data.
Data inputs and clock enable inputs are fully edge–triggered
and must be stable only one setup time before the
low–to–high clock transition.
The master reset (MR) is an active–high asynchronous
input. When the MR is high, all four flip–flops are reset
(cleared) independently of any other input condition.
The 3–state output buffers are controlled by a 2–input NOR
gate. When both output enable (OE0 and OE1) inputs are
low, the data in the register is presented at the Q output.
When one or both OE inputs are high, the outputs are forced
to a high impedance ”off” state.
The 3–state output buffers are completely independent of
the register operation; the OE transition does not affect the
clock and reset operations.
TYPE
TYPICAL f
max
125MHz
TYPICAL SUPPLY CURRENT (TOTAL)
74F173
23mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F173N
PKG DWG #
16–pin plastic DIP
SOT38-4
16–pin plastic SO
N74F173D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
20
μ
A/0.6mA
CP
Clock input
1.0/1.0
E0, E1
Clock enable inputs
1.0/1.0
MR
Master reset input
1.0/1.0
OE0, OE1
Output enable inputs
1.0/1.0
Q0 – Q3
Data outputs
750/80
15mA/48mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
μ
A in the high state and 0.6mA in the low state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74F174SCX | Hex D-Type Flip-Flop |
| 74F174SJX | Hex D-Type Flip-Flop |
| 74F175SCX | Quad D-Type Flip-Flop |
| 74F175SJX | Quad D-Type Flip-Flop |
| 74F174 | Hex D flip-flops |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74F174 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Hex D Flip-Flop with Master Reset |
| 74F174_00 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Hex D-Type Flip-Flop with Master Reset |
| 74F174_XHF3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F174D | 制造商:Motorola 功能描述:74F174 MOT S1I2A |
| 74F174DC | 制造商:Fairchild Semiconductor Corporation 功能描述:Flip Flop, Hex, D Type, 16 Pin, Ceramic, DIP 制造商:Freescale Semiconductor 功能描述:Flip Flop, Hex, D Type, 16 Pin, Ceramic, DIP |
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