參數(shù)資料
型號: 74F175SJX
元件分類: 通用總線功能
英文描述: Quad D-Type Flip-Flop
中文描述: 四D型觸發(fā)器
文件頁數(shù): 2/7頁
文件大?。?/td> 77K
代理商: 74F175SJX
www.fairchildsemi.com
2
7
Unit Loading/Fan Out
Functional Description
The 74F174 consists of six edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The 74F174 is
useful for applications where the true output only is
required and the Clock and Master Reset are common to
all storage elements.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
Output I
OH
/I
OL
20
μ
A/
0.6 mA
20
μ
A/
0.6 mA
20
μ
A/
0.6 mA
1 mA/20 mA
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
D
0
D
5
CP
MR
Q
0
Q
5
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
Inputs
Outputs
MR
CP
D
n
Q
n
L
X
X
L
H
H
H
H
L
L
相關(guān)PDF資料
PDF描述
74F174 Hex D flip-flops
74F174 Hex D Flip-Flop with Master Reset
74F174PC Hex D Flip-Flop with Master Reset
74F174SC Hex D Flip-Flop with Master Reset
74F174SJ Hex D Flip-Flop with Master Reset
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