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參數(shù)資料
| 型號： | 74F1763 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Intelligent DRAM controller IDC |
| 中文描述： | IDC的智能內(nèi)存控制器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 117K |
| 代理商： | 74F1763 |
Philips Semiconductors
Product specification
74F1763
Intelligent DRAM controller (IDC)
1999 Jan 08
10
TIMING DIAGRAMS (Continued)
34
NOTE 1
: REQ input is a don’t care during a memory refresh cycle. If REQ is asserted during a refresh cycle, it will be recognized at the first rising CP clock edge, following the refresh
cycle and its associated RAS precharge time (see Figure 4).
NOTE 2
: RA0–9 and CA0–9 address inputs may be latched at anytime during a memory refresh cycle. However, a memory access cycle will not begin until after the completion of the
refresh cycle.
NOTE 3
: RA0–9 and CA0–9 if in the transparent mode do not propogate to the MA0–9 outputs during a refresh cycle.
NOTE 4
: MA0–9 output will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.
CP
REQ
GNT
ALE
RA0–9,
CA0–9
MA0–9
RAS
CAS
DTACK
SF01405
NOTE 1
NOTE 2
NOTE 4
REFRESH
ADDR.
REFRESH
ADDR.
NEXT REFRESH ADDRESS
3-STATE
33
34
33
35
20
20
36
PRECHRG = 1
PRECHRG = 1
PRECHRG = 0
PRECHRG = 0
Figure 3. Refresh cycle timing following a memory access cycle
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相關代理商/技術參數(shù) |
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| 74F1779 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit bidirectional binary counter -State |
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| 74F1808N | 制造商:NXP Semiconductors 功能描述: |
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