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參數資料
| 型號： | 74F1763 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Intelligent DRAM controller IDC |
| 中文描述： | IDC的智能內存控制器 |
| 文件頁數： | 7/16頁 |
| 文件大?。?/td> | 117K |
| 代理商： | 74F1763 |
Philips Semiconductors
Product specification
74F1763
Intelligent DRAM controller (IDC)
1999 Jan 08
7
AC ELECTRICAL CHARACTERISTICS
LIMITS
NO
PARAMETER
TEST
CONDITIONS
T
A
= 25 C
V
CC
= +5.0V
C
L
= 300pF
R
L
= 70
TYP
10%
T
A
= 0 C to +70 C
V
CC
= +5.0V
C
L
= 300pF
RL = 70
10%
UNIT
MIN
MAX
MIN
MAX
1
CP clock period (tcp)
10
10
ns
2
CP clock low time
5
5
ns
3
CP clock high time
5
5
ns
4
RCP clock period
100
100
ns
5
RCP clock low time
10
10
ns
6
RCP clock high time
10
10
ns
7
Setup time REQ( ) to CP( )
4
2
4
ns
8
REQ High hold time after CP( )
1
0
0
ns
9
REQ High pulse width
2
1/2tcp + 5
1/2tcp + 5
1/2tcp + 5
1/2tcp + 5
1/2tcp + 5
ns
10
Propagation delay CP( ) to GNT
High
8.5
11
13.5
8.5
15.5
ns
11
Propagation delay REQ( ) to GNT
Low
8.5
10.5
13
8.5
14
ns
12
ALE pulse width Low
4
1
4
ns
13
RA0–9, CA0–9 High or Low setup to
ALE( )
2
0
2
ns
14
ALE( ) to RA0–9, CA0–9 High or
Low hold
1
0
1
ns
15
Propagation delay RA0–9, CA0–9
High or Low to MA0–9
3
ALE Low
4
7.5
11
4
14
ns
16
Propagation delay ALE( ) to MA0–9
5.5
8.5
13
5.5
15
ns
17
Propagation delay CP( ) to RAS( )
8.5
10.5
12.5
8.5
14
ns
18
RAS( ) to MA0–9 (column address)
skew
HLDROW = 1
1/2tcp – 2
1/2tcp + 2
1/2tcp + 5.5
1/2tcp – 2.5
1/2tcp + 7
ns
19
RAS( ) to MA0–9 (column address)
skew
HLDROW = 0
1tcp – 2
1tcp + 2
1tcp + 5.5
1tcp – 2.5
1tcp + 7
ns
20
RAS( ) to RAS( ) skew
PAGE = 1
4tcp + 1.5
4tcp + 3.5
4tcp + 6
4tcp + 1
4tcp + 6.5
ns
21
Propagation delay CP( ) to RAS( )
12
14
16.5
12
18.5
ns
22
Propagation delay REQ( ) to
RAS( )
4
14.5
17.5
20
14
24
ns
23
Propagation delay CP( ) to CAS( )
6
8
10
6
11
ns
24
Propagation delay PAGE( ) to
RAS( )
4
10
12.5
15
10
17
ns
25
RAS( ) to CAS( ) skew
1.5tcp–4.5
1.5tcp–2.5
1.5tcp–0.5
1.5tcp–5.5
1.5tcp
ns
26
Propagation delay REQ( ) to CAS( )
10
12
15
10
17
ns
27
MA0–9 (column address) to CAS( )
skew
1tcp – 8
1tcp – 4
1tcp – 0.5
1tcp – 9
1tcp – 0.5
ns
28
MA0–9 (column address) to CAS( )
skew
HLDROW = 0
1/2tcp – 8
1/2tcp – 4
1/2tcp – 0.5
1/2tcp – 9
1/2tcp – 0.5
ns
29
Set-up time PAGE( ) to CP( )
2
2
ns
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|---|---|
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相關代理商/技術參數 |
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|---|---|
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| 74F1805 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hex 2-input NOR drivers |
| 74F1808 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hex 2-input AND drivers |
| 74F1808N | 制造商:NXP Semiconductors 功能描述: |
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