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參數(shù)資料
| 型號(hào)： | 74F525SCX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable Counter |
| 中文描述： | F/FAST SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 184K |
| 代理商： | 74F525SCX |
Timing Diagrams
TL/F/9547–5
j
With XTR HIGH, the rising edge of CP loads data from the latches to the counter.
k
With XTR LOW, the rising edge of CP begins count-down cycle.
l
When the count reaches zero, Q goes HIGH, and Q/2 toggles state.
m
The next occurrence of XTR clears Q.
FIGURE 1. MODE 0 and MODE 1 (Inverse Output of Mode 0)
M
n
e
000, 001
TL/F/9547–6
j
With XTR HIGH, the rising edge of CP loads data from the latches to the counter.
k
With XTR LOW, the rising edge of CP begins the count-down cycle.
l
When the count reaches zero, Q goes HIGH for one period of CP, and Q/2 toggles state.
FIGURE 2. MODE 2 and MODE 3 (Inverse Output of Mode 2)
M
n
e
010, 011
TL/F/9547–7
FIGURE 3. MODE 4 and MODE 5
M
n
e
100, 101
j
With XTR HIGH, the rising edge of CP loads data from the latches into the counter.
k
With XTR LOW, the rising edge of CP begins the count-down.
l
With XTR HIGH, during count-down, the rising edge of CP does nothing.
m
When the count reaches zero, Q goes HIGH for one clock cycle and Q/2 toggles state.
Note:
Once the count reaches zero, the counter can be reloaded with XTR HIGH.
4
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