參數(shù)資料
型號(hào): 74FCT162652CTPVCT
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: 16-Bit Registered Transceivers
中文描述: 16位注冊(cè)收發(fā)器
文件頁數(shù): 7/10頁
文件大小: 77K
代理商: 74FCT162652CTPVCT
CY74FCT16652T
CY74FCT162652T
7
Switching Characteristics
Over the Operating Range
[17]
Parameter
Description
CY74FCT16652AT
CY74FCT162652AT
Unit
Min.
Max.
Fig. No.
[18]
t
PLH
t
PHL
t
PZH
t
PHL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
t
H
t
W
t
SK(O)
Propagation Delay Bus to Bus
1.5
6.3
ns
1, 3
Output Enable Time OEAB or OEBA to Bus
1.5
9.8
ns
1, 7, 8
Output Disable Time OEAB or OEBA to Bus
1.5
6.3
ns
1, 7, 8
Propagation Delay Clock to Bus
1.5
6.3
ns
1, 5
Propagation Delay SBA or SAB to Bus
1.5
7.7
ns
1, 5
Set-Up time HIGH or LOW Bus to Clock
2.0
ns
4
Hold Time HIGH or LOW Bus to Clock
1.5
ns
4
Clock Pulse Width HIGH or LOW
Output Skew
[19]
5.0
ns
5
0.5
ns
Parameter
Description
CY74FCT16652CT
CY74FCT162652CT
CY74FCT16652ET
CY74FCT162652ET
Unit
Min.
Max.
Min.
Max.
Fig. No.
[18]
t
PLH
t
PHL
t
PZH
t
PHL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
Propagation Delay
Bus to Bus
1.5
5.4
1.5
3.8
ns
1, 3
Output Enable Time
OEAB or OEBA to Bus
1.5
7.8
1.5
4.8
ns
1, 7, 8
Output Disable Time
OEAB or OEBA to Bus
1.5
6.3
1.5
4.0
ns
1, 7, 8
Propagation Delay
Clock to Bus
1.5
5.7
1.5
3.8
ns
1, 5
Propagation Delay
SBA or SAB to Bus
1.5
6.2
1.5
4.2
ns
1, 5
Set-Up Time
HIGH or LOW
Bus to Clock
2.0
2.0
ns
4
t
H
Hold Time
HIGH or LOW
Bus to Clock
1.5
0.0
ns
4
t
W
Clock Pulse Width
HIGH or LOW
Output Skew
[19]
5.0
3.0
ns
5
t
SK(O)
0.5
0.5
ns
Notes:
17. Minimum limits are specified, but not tested, on propagation delays.
18. See “Parameter Measurement Information” in the General Information section.
19. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
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