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參數(shù)資料
| 型號： | 74GTLP22034DGVRE4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH |
| 中文描述： | 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開登記LVTTL港口及反饋路徑 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 366K |
| 代理商： | 74GTLP22034DGVRE4 |
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C – JUNE 2001 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
TI-OPC
Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC
Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
AO Outputs Have Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Open-Drain Outputs
(100 mA)
LVTTL Outputs (–12 mA/12 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLP22034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP
and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of
data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and
diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP’s reduced output swing (
<
1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11
.
The AO outputs, which are designed to sink up to 12 mA, include equivalent 26-
resistors to reduce overshoot
and undershoot.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
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IMODE1
AI1
AO1
GND
AI2
AO2
V
CC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
V
CC
AO7
AI7
GND
AO8
AI8
OMODE0
IMODE0
BIAS V
CC
B1
GND
OEAB
B2
ERC
OEAB
B3
GND
CLKAB/LEAB
B4
B5
CLKBA/LEBA
GND
B6
OEBA
V
CC
B7
LOOPBACK
GND
B8
V
REF
OMODE1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74GTLP22034DGVRG4 | 功能描述:特定功能邏輯 8B LVTTL-GTLP Adj- Edge-Rate Reg Trans RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| 74GTLPH1612DGGRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 18-Bit LVTTL/GTLP Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74GTLPH1612DGGRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL-GTLP Adj- Edge-Rate Univ Bus RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| 74GTLPH1616DGGRE4 | 功能描述:通用總線函數(shù) 17-Bit LVTTL-to-GTLP Univ Bus Trans RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74GTLPH1616DGGRG4 | 功能描述:通用總線函數(shù) 17B LVTTL-GTLP Adj- Edge-Rate Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時(shí)間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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