參數(shù)資料
型號： 74GTLP22034DGVRE4
廠商： Texas Instruments, Inc.
英文描述： 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
中文描述： 8位LVTTL至GTLP可調(diào)EDGE的速率收發(fā)器劈開登記LVTTL港口及反饋路徑
文件頁數(shù)： 12/20頁
文件大?。?/td> 366K
代理商： 74GTLP22034DGVRE4
SN74GTLP22034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES355C
–
JUNE 2001
–
REVISED SEPTEMBER 2001
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
tPLH
tPHL
tPLH
tPHL
LOOPBACK
AO
2.5
6.1
ns
–
2
5.1
AI
AO
1
5.7
ns
(loopback high)
–
1
5.4
Rise time B port outputs (20% to 80%)
Rise time, B-port outputs (20% to 80%)
Slow
2.8
tr
Fast
1.5
ns
Rise time, AO (10% to 90%)
5.5
Fall time B port outputs (80% to 20%)
Fall time, B-port outputs (80% to 20%)
Slow
3
tf
Fast
1.8
4.5
ns
Fall time, AO (90% to 10%)
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25
°
C.
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
§
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
tsk(LH)
tsk(HL)
AI
B
Slow
0.5
1
ns
0.5
1
AI
B
Fast
0.4
0.9
ns
0.4
0.9
CLKAB/LEAB
B
Slow
0.5
1
ns
0.5
1
CLKAB/LEAB
B
Fast
0.4
0.9
ns
0.4
0.9
AI
B
Slow
1.4
2
tk(t)
Fast
0.6
1.4
ns
tsk(t)
CLKAB/LEAB
B
Slow
1.8
2.5
Fast
0.9
1.8
Slow (ERC = L) and Fast (ERC = H)
All typical values are at VCC = 3.3 V, TA = 25
°
C.
§
Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
tsk(LH)/tsk(HL) and tsk(t)
–
Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
相關(guān)PDF資料
PDF描述
74H1G66 SINGLE BILATERAL SWITCH
74H1G66S SINGLE BILATERAL SWITCH
74H76 Cardmaster Enclosure; NEMA Type:4X; Enclosure Material:Polycarbonate; External Height:4.2"; External Width:6.3"; External Depth:6.5"; Enclosure Color:Light Gray; Approval Bodies:UL, cUL; Cover Color:Smoked Transparent
74HC01 Quad. 2-input NAND Gates (with open drain outputs)
74HC05 HEX INVERTER OPEN DRAIN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74GTLP22034DGVRG4 功能描述:特定功能邏輯 8B LVTTL-GTLP Adj- Edge-Rate Reg Trans RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
74GTLPH1612DGGRE4 功能描述:轉(zhuǎn)換 - 電壓電平 18-Bit LVTTL/GTLP Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
74GTLPH1612DGGRG4 功能描述:轉(zhuǎn)換 - 電壓電平 18B LVTTL-GTLP Adj- Edge-Rate Univ Bus RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
74GTLPH1616DGGRE4 功能描述:通用總線函數(shù) 17-Bit LVTTL-to-GTLP Univ Bus Trans RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74GTLPH1616DGGRG4 功能描述:通用總線函數(shù) 17B LVTTL-GTLP Adj- Edge-Rate Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*