參數(shù)資料
型號(hào): 74HC193PW,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 10/30頁(yè)
文件大?。?/td> 0K
描述: IC 4BIT BINARY UP/DN CNT 16TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 96
系列: 74HC
邏輯類(lèi)型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 49MHz
觸發(fā)器類(lèi)型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
其它名稱(chēng): 74HC193PW
74HC193PW-ND
935188980112
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
18 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
11. Waveforms
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
001aag413
CPU, CPD
input
VI
GND
VOH
VOL
Qn output
tPHL
tPLH
tW
VM
1/fmax
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. The clock (CPU, CPD) to terminal count output (TCU,TCD) propagation delays
001aag414
CPU, CPD
input
TCU, TCD
output
tPHL
VI
GND
VOH
VOL
tPLH
VM
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