參數(shù)資料
型號(hào): 74HC193PW,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 6/30頁(yè)
文件大?。?/td> 0K
描述: IC 4BIT BINARY UP/DN CNT 16TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 96
系列: 74HC
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 4
復(fù)位: 異步
計(jì)時(shí): 同步
計(jì)數(shù)速率: 49MHz
觸發(fā)器類型: 正邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
其它名稱: 74HC193PW
74HC193PW-ND
935188980112
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
14 of 30
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
tpd
propagation
delay
Dn to TCU,Dnto
TCD; see Figure 14
VCC = 2.0 V
-
80
290
-
365
-
435
ns
VCC = 4.5 V
-
29
58
-
73
-
87
ns
VCC = 6.0 V
-
23
49
-
62
-
74
ns
tTHL
HIGH to LOW
output transition
time
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC =4.5 V
-
7
15
-
19
-
22
ns
VCC =6.0 V
-
6
13
-
16
-
19
ns
tTLH
LOW to HIGH
output transition
time
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC =4.5 V
-
7
15
-
19
-
22
ns
VCC =6.0 V
-
6
13
-
16
-
19
ns
tW
pulse width
CPU, CPD (HIGH
or LOW); see
VCC = 2.0 V
100
22
-
125
-
150
-
ns
VCC =4.5 V
20
8
-
25
-
30
-
ns
VCC =6.0 V
17
6
-
21
-
26
-
ns
MR (HIGH); see
VCC = 2.0 V
100
25
-
125
-
150
-
ns
VCC =4.5 V
20
9
-
25
-
30
-
ns
VCC =6.0 V
17
7
-
21
-
26
-
ns
PL (LOW); see
VCC = 2.0 V
100
19
-
125
-
150
-
ns
VCC =4.5 V
20
7
-
25
-
30
-
ns
VCC =6.0 V
17
6
-
21
-
26
-
ns
trec
recovery time
PL to CPU, CPD;
VCC =2.0 V
50
8
-
65
-
75
-
ns
VCC =4.5 V
10
3
-
13
-
15
-
ns
VCC =6.0 V
9
2
-
11
-
13
-
ns
MR to CPU, CPD;
VCC =2.0 V
50
0
-
65
-
75
-
ns
VCC =4.5 V
10
0
-
13
-
15
-
ns
VCC =6.0 V
9
0
-
11
-
13
-
ns
Table 8.
Dynamic characteristics type 74HC193 …continued
Symbol
Parameter
Conditions
25
C
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
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