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參數(shù)資料
| 型號： | 74HC40105 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit x 16-word FIFO register |
| 中文描述： | 4位× 16字FIFO寄存器 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 74HC40105 |
1998 Jan 23
17
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words
×
4 bits
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, date arrives at the output of FIFO
A
. Due to SO
A
being HIGH, a DOR pulse is
generated. The requirements of SI
B
and D
nB
are satisfied by the DOR
A
pulse width and the timing between the rising
edge of DOR
A
and Q
nA
. After a second ripple through delay, data arrives at the output of FIFO
B
.
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
R
pulse, when both FIFOs are initially
full. After a bubble-up delay a DIR
R
pulse is generated, which acts as a SO
A
pulse for FIFO
A
. One word is transferred
from the output of FIFO
A
to the input of FIFO
B
. The requirements of the SO
A
pulse for FIFO
A
is satisfied by the pulse
width of DOR
B
. After a second bubble-up delay an empty space arrives at D
nA
, at which time DIR
A
goes HIGH.
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
Fig.19 Cascading for increased word capacity; 32 words
×
4 bits.
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFO
A
and FIFO
B
. Fig.22 gives an
overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC40105D | 功能描述:寄存器 4BX16W FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC40105D,652 | 功能描述:寄存器 4BX16W FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC40105D,653 | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HC40105D652 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| 74HC40105DB | 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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