參數(shù)資料
型號(hào)： 74HC40105
廠商： NXP Semiconductors N.V.
英文描述： 4-bit x 16-word FIFO register
中文描述： 4位× 16字FIFO寄存器
文件頁(yè)數(shù)： 19/25頁(yè)
文件大?。?/td> 200K
代理商： 74HC40105
1998 Jan 23
19
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Fig.22 Waveforms
showing the
functionally and
inter-
communication
between two
FIFOs
(refer to Fig.19).
Note to
Fig.22
Sequence 1 (Both FIFOs empty, starting shift-in process):
After a MR pulse has been applied FIFO
A
and FIFO
B
are
empty. The DOR flags of FIFO
A
and FIFO
B
go LOW due
to no valid data being present at the outputs. The DIR flags
are set HIGH due to the FIFOs being ready to accept data.
SO
B
is held HIGH and two SI
A
pulses are applied (1).
These pulses allow two data words to ripple through to the
output stage of FIFO
A
and to the input stage of FIFO
B
(2).
When data arrives at the output of FIFO
B
, a DOR
B
pulse is
generated (3). When SO
B
goes LOW, the first bit is shifted
out and a second bit ripples through to the output after
which DOR
B
goes HIGH (4).
Sequence 2 (FIFO
B
runs full):
After the MR pulse, a series of 16 SI pulses are applied.
When 16 words are shifted in, DIR
B
remains LOW due to
FIFO
B
being full (5). DOR
A
goes LOW due to FIFO
A
being
empty.
Sequence 3 (FIFO
A
runs full):
When 17 words are shifted in, DOR
A
remains HIGH due to
valid data remaining at the output of FIFO
A
. Q
nA
remains
HIGH, being the polarity of the 17th data word (6). After the
32th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
Sequence 4 (Both FIFOs full, starting shift-out process):
SI
A
is held HIGH and two SO
B
pulses are applied (8).
These pulses shift out two words and thus allow empty
locations to bubble-up to the input stage of FIFO
B
, and
proceed to FIFO
A
(9). When the first empty location arrives
at the input of FIFO
A
, a DIR
A
pulse is generated (10) and
a new word is shifted into FIFO
A
. SI
A
is made LOW and
now the second empty location reaches the input stage of
FIFO
A
, after which DIR
A
remains HIGH (11).
Sequence 5 (FIFO
A
runs empty):
At the start of sequence 5 FIFO
A
contains 15 valid words
due to two words being shifted out and one word being
shifted in sequence 4. An additional series of SO
B
pulses
are applied. After 15SO
B
pulses, all words from FIFO
A
are
shifted into FIFO
B
. DOR
A
remains LOW (12).
Sequence 6 (FIFO
B
runs empty):
After the next SO
B
pulse, DIR
B
remains HIGH due to the
input stage of FIFO
B
being empty (13). After another 15
SO
B
pulses, DOR
B
remains LOW due to both FIFOs being
empty (14). Additional SO
B
pulses have no effect. The last
word remains available at the output Q
n
.
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參數(shù)描述
74HC40105D 功能描述:寄存器 4BX16W FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74HC40105D,652 功能描述:寄存器 4BX16W FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74HC40105D,653 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
74HC40105D652 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述:
74HC40105DB 功能描述:寄存器 4-BIT X 16 WORD FIFO REGISTER RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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