參數(shù)資料
型號(hào): 74HC4024DB,118
廠(chǎng)商: NXP Semiconductors
文件頁(yè)數(shù): 1/19頁(yè)
文件大小: 0K
描述: IC 7STAGE BINARY RIPPLE 14SSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,000
系列: 74HC
邏輯類(lèi)型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 7
復(fù)位: 異步
計(jì)數(shù)速率: 90MHz
觸發(fā)器類(lèi)型: 負(fù)邊沿
電源電壓: 2 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 14-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 14-SSOP
包裝: 帶卷 (TR)
其它名稱(chēng): 74HC4024DB-T
74HC4024DB-T-ND
935189980118
1.
General description
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the
circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2.
Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 Cto+80 C and from 40 Cto+125 C.
3.
Applications
Frequency dividing circuits
Time delay circuits.
74HC4024
7-stage binary ripple counter
Rev. 7 — 31 October 2013
Product data sheet
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