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參數(shù)資料
| 型號： | 74HC4024DB,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 7STAGE BINARY RIPPLE 14SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 74HC |
| 邏輯類型： | 二進(jìn)制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 7 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 90MHz |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74HC4024DB-T 74HC4024DB-T-ND 935189980118 |
74HC4024
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 31 October 2013
7 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
tpd
propagation delay
CP to Q0; see Figure 6
VCC = 2.0 V
-
47
175
ns
VCC = 4.5 V
-
17
35
ns
VCC = 6.0 V
-
14
30
ns
VCC =5.0 V; CL =15pF
-
14
-
ns
Qn to Qn+1; see Figure 6
VCC = 2.0 V
-
25
80
ns
VCC = 4.5 V
-
9
16
ns
VCC = 6.0 V
-
7
14
ns
tPHL
HIGH to LOW
propagation delay
MR to Q0; see Figure 6
VCC = 2.0 V
-
63
200
ns
VCC = 4.5 V
-
23
40
ns
VCC = 6.0 V
-
18
34
ns
tt
transition time
see Figure 6
VCC = 2.0 V
-
19
75
ns
VCC = 4.5 V
-
7
15
ns
VCC = 6.0 V
-
6
13
ns
tW
pulse width
CP HIGH or LOW; see Figure 6
VCC = 2.0 V
8017-
ns
VCC = 4.5 V
16
6
-
ns
VCC = 6.0 V
14
5
-
ns
MR HIGH; see Figure 6
VCC = 2.0 V
8022-
ns
VCC = 4.5 V
16
8
-
ns
VCC = 6.0 V
14
6
-
ns
trec
recovery time
MR to CP; see Figure 6
VCC = 2.0 V
50
6
-
ns
VCC = 4.5 V
10
2
-
ns
VCC = 6.0 V
9
2
-
ns
fmax
maximum frequency
CP; see Figure 6
VCC = 2.0 V
6.0
27
-
MHz
VCC = 4.5 V
3082-
MHz
VCC = 6.0 V
3598-
MHz
VCC =5.0 V; CL =15pF
-
90
-
MHz
CPD
power dissipation
capacitance
VI = GND to VCC
[3] -25
-pF
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