參數(shù)資料
型號(hào): 74LV74PW,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 18/19頁(yè)
文件大?。?/td> 0K
描述: IC DUAL D FF POSEDG TRIG 14TSSOP
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 2,400
系列: 74LV
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個(gè)元件的位元數(shù): 1
頻率 - 時(shí)鐘: 56MHz
觸發(fā)器類型: 正邊沿
輸出電流高,低: 12mA,12mA
電源電壓: 1 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
74LV74
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 9 September 2013
8 of 19
NXP Semiconductors
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V): for test circuit, see Figure 8
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation
delay
nCP to nQ, nQ; see Figure 6
VCC = 1.2 V
-
70
-
ns
VCC = 2.0 V
-
24
44
-
56
ns
VCC = 2.7 V
-
18
28
-
41
ns
VCC = 3.0 V to 3.6 V
-13
26
-
33
ns
VCC = 3.3 V; CL = 15 pF
-
11
-
ns
VCC = 4.5 V to 5.5 V
-9.5
17
-
23
ns
nSD to nQ, nQ; see Figure 7
VCC = 1.2 V
-
90
-
ns
VCC = 2.0 V
-
31
46
-
58
ns
VCC = 2.7 V
-
23
34
-
43
ns
VCC = 3.0 V to 3.6 V
-17
27
-
34
ns
VCC = 3.3 V; CL = 15 pF
-
14
-
ns
VCC = 4.5 V to 5.5 V
-12
19
-
24
ns
nRD to nQ, nQ; see Figure 7
VCC = 1.2 V
-
90
-
ns
VCC = 2.0 V
-
31
46
-
58
ns
VCC = 2.7 V
-
23
34
-
43
ns
VCC = 3.0 V to 3.6 V
-17
27
-
34
ns
VCC = 3.3 V; CL = 15 pF
-
14
-
ns
VCC = 4.5 V to 5.5 V
-12
19
-
24
ns
tW
pulse width
nCP input HIGH to LOW;
VCC = 2.0 V
34
10
-
41
-
ns
VCC = 2.7 V
25
8
-
30
-
ns
VCC = 3.0 V to 3.6 V
20
7
-
24
-
ns
VCC = 4.5 V to 5.5 V
15
6
-
18
-
ns
nSD or nRD pulse width LOW;
VCC = 2.0 V
34
10
-
41
-
ns
VCC = 2.7 V
25
8
-
30
-
ns
VCC = 3.0 V to 3.6 V
20
7
-
24
-
ns
VCC = 4.5 V to 5.5 V
15
6
-
18
-
ns
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