參數(shù)資料
型號(hào)： 74LVC1G125
廠商： NXP Semiconductors N.V.
英文描述： Bus buffer/line driver; 3-state
中文描述： 總線緩沖器/線路驅(qū)動(dòng)器，三態(tài)
文件頁(yè)數(shù)： 8/17頁(yè)
文件大小： 91K
代理商： 74LVC1G125
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
8 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
t
h
hold time D to CP
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 3.3 V
0.0
0.3
0.5
-
-
-
0.2
-
-
-
-
-
-
ns
ns
ns
ns
ns
[2]
1.2
0.5
f
max
maximum clock pulse
frequency
80
175
175
125
-
-
300
-
14
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
pF
[2]
175
200
C
PD
power dissipation
capacitance
[3] [4]
-
T
amb
=
40
°
C to +125
°
C
t
PHL
, t
PLH
propagation delay CP to Q
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
1.5
1.0
1.0
0.5
0.5
-
-
-
-
-
17
9.0
9.0
7.5
5.5
ns
ns
ns
ns
ns
propagation delay MR to Q
1.5
1.0
1.0
0.5
0.5
-
-
-
-
-
17
9.0
9.0
7.5
5.5
ns
ns
ns
ns
ns
t
W
clock pulse width HIGH or
LOW
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
master reset pulse width
LOW
6.2
2.7
2.7
2.7
2.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
Table 8:
GND = 0 V; see
Figure 8
Symbol
Dynamic characteristics
…continued
Parameter
Conditions
Min
Typ
Max
Unit
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