參數(shù)資料
型號: 74LVTH125SJ
廠商: Fairchild Semiconductor
文件頁數(shù): 8/9頁
文件大?。?/td> 0K
描述: IC BUFF TRI-ST QD LOW V 14SOP
標準包裝: 47
系列: 74LVTH
邏輯類型: 緩沖器/線路驅動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 1
輸出電流高,低: 32mA,64mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
供應商設備封裝: 14-SOIC
包裝: 管件
1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVTH125 Rev. 1.4.0
8
74L
VTH125
Lo
w
V
olta
g
e
Quad
Buff
er
with
3-ST
A
TE
Outputs
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00
°TOP & BOTTOM
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
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