參數(shù)資料
型號(hào)： 74VHC112SJX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： J-K-Type Flip-Flop
中文描述： AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝： 5.30 MM, EIAJ TYPE2, SOP-16
文件頁(yè)數(shù)： 4/7頁(yè)
文件大?。?/td> 70K
代理商： 74VHC112SJX
www.fairchildsemi.com
4
7
AC Electrical Characteristics
Note 3:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
/4 (per F/F), and the total C
PD
when n pcs of the Flip-Flop operate can
be calculated by the following equation: C
PD
(total)
=
30
+
14 n
AC Operating Requirements
Note 4:
V
CC
is 3.3
±
0.3V or 5.0
±
0.5V
Symbol
Parameter
V
CC
(V)
T
A
=
25
°
C
Typ
150
120
200
T
A
=
40
°
C to
+
85
°
C
Min
100
80
135
Units
Conditions
Min
110
90
150
Max
Max
f
MAX
Maximum Clock
Frequency
3.3
±
0.3
MHz
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
(Note 3)
5.0
±
0.5
MHz
120
185
8.5
10.0
110
1.0
1.0
t
PLH
t
PHL
Propagation Delay
3.3
±
0.3
11.0
15.0
13.4
16.5
ns
Time (CP to Q
n
or Q
n
)
5.0
±
0.5
5.1
6.3
7.3
10.5
1.0
1.0
8.8
12.0
ns
t
PLH
t
PHL
Propagation Delay Time
3.3
±
0.3
6.7
9.7
10.2
13.5
1.0
1.0
11.7
15.0
ns
(PR or CLR to Q
n
or Q
n
)
5.0
±
0.5
4.6
6.4
4
6.7
9.5
10
1.0
1.0
8.0
11.0
10
ns
C
IN
C
PD
Input Capacitance
pF
Power Dissipation
Capacitance
18
pF
Symbol
Parameter
V
(Note 4)
(V)
3.3
5.0
3.3
T
A
=
25
°
C
Typ
T
A
=
40
°
C to
+
85
°
C
Guaranteed Minimum
Units
t
W
Minimum Pulse Width
(CP or CLR or PR)
Minimum Setup Time
5.0
5.0
5.0
5.0
5.0
5.0
ns
t
S
ns
(J
n
or K
n
to CP
n
)
Minimum Hold Time
(J
n
or K
n
to CP
n
)
Minimum Recovery Time
(CLR or PR to CP)
5.0
3.3
5.0
4.0
1.0
1.0
4.0
1.0
1.0
t
H
ns
t
REC
3.3
5.0
6.0
5.0
6.0
5.0
ns
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