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參數(shù)資料
| 型號： | 75N42102 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | NETWORK SEARCH ENGINE 32K x 72 Entries |
| 中文描述： | 網(wǎng)絡搜索引擎32K的× 72項 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 437K |
| 代理商： | 75N42102 |
APRIL 2004
DSC-6457/00
1
2004 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
NETWORK SEARCH ENGINE
32K x 72 Entries
Datasheet
Brief
75N42102
Device Description
IDT provides proven, industry-leading network search engines
(NSEs) that enable and accelerate the intelligent processing of network
services in communications equipment. As a part of the complete IDT
classification subsystemthat includes content inspection engines, the IDT
famly of NSEs delivers high-performance, feature-rich, easy-to-use,
integrated search accelerators.
The IDT 75N42102 NSE is a high performance, low cost, full-ternary
32K x 72 entry device. Each entry location in the NSE has both a Data
entry and an associated Mask entry. The NSE devices integrate content
addressable memory (CAM) technology with high-performance logic.
The device can performLookup operations plus Read and Write
maintenance operations.
The IDT 75N42102 NSE device has a bi-directional bus that is a
multiplexed address and data bus that can support up to 200 mllion
sustained searches per second. This device offers the ability to simulta-
neously search in mutually exclusive databases substantially increasing
the NSE search rate. This device can be configured to enable multiple
width lookups from40 to 288 bits wide. The IDT 75N42102 requires a
1.5-volt V
DD1
supply and a 2.5-volt V
DD2
supply.
The IDT 75N42102 NSE utilizes the latest high-performance 1.5V
CMOS processing technology and is packaged in a JEDEC Standard,
thermally enhanced, 304 pin low profile Ball Grid Array.
To request the full IDT75N42102 datasheet, please contact your local
IDT Sales Representative or call 1-800-345-7015
6457drw02
Optional
Figure 1.0 ASIC / Compatible NSE / SRAMconfiguration
N
ASIC
or
FPGA
ZBT
or
Sync SRAM
IDT 75N42102
Network Search
Engine
Configuration Registers
and
Ram Control Circuits
CLOCK
PHASE
CCLK
÷ 2
SRAM CONTROL
ASIC FEEDBACK
P
R
I
O
R
I
T
Y
E
N
C
O
D
E
R
S
I
Z
E
L
O
G
I
C
D
E
C
O
D
E
Address
MATCHOUT
REQSTB
R/W
6457 drw 01
RESET
Command
Bus
Request
Data
Bus
Index
Bus
NSE
REQUEST
BUS
NSE
RESPONSE
BUS
MATCHIN
CONFIGIN
Bypass
DATA
ARRAY
Instruction
Global Mask Registers
Result Register
CONFIGOUT
Block Diagram
System Configurations
The IDT NSEs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a systemconfiguration as shown in Figure 1.0 may be realized.
In this configuration, the NSE interfaces directly to an ASIC/ FPGA for
lookups and routes an Index to an associated SRAMdevice, which
supplies the next hop address via an SRAMData Bus to the ASIC. The
NSE provides the required control signals to directly hookup to ZBT
or Synchronous Pipeline Burst SRAM. Lookup results can also be fed
directly back to the ASIC/ FPGA without the use of external SRAM Control
of the associated handshake signals is provided by all NSEs to adapt to
either configuration.
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