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參數(shù)資料
| 型號(hào)： | 75N42102 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | NETWORK SEARCH ENGINE 32K x 72 Entries |
| 中文描述： | 網(wǎng)絡(luò)搜索引擎32K的× 72項(xiàng) |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 437K |
| 代理商： | 75N42102 |
2
Network Search Engine 32K x 72 Entries Datasheet Brief 75N42102
SRAMInterface
The NSE provides all required address and control signals for a
glueless SRAMinterface. The NSE provides a pipelined bypass path for
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipelining of the data to and fromthe SRAM.
Registers
There are four basic types of registers supported:
■
Configuration Registers are used at initialization to define the
segmentation of the entries, timng of outputs and the SRAMinterface.
■
Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
■
Search Result Registers are used to store the resulting index of
a search froma Lookup operation.
■
Reply Width Registers are used with Lookup operations.
Functional Highlights
Data and Mask Array
The NSE has Data cell entries and associ-
ated Mask cell entries as shown in Fig. 1.1. This
combination of Data and Mask cell entries en-
ables the NSE to store 0, 1 or X, making it a full
ternary Network Search Engine. During a
lookup operation, both arrays are used along
with a Global Mask Register to find a match to a
requested data word.
Figure 1.1
Bus Interface
The NSE utilizes a dual bus interface consisting of the NSE Request
Bus and the NSE Response Bus.
The NSE Request Bus is comprised of the Command Bus and the
Request Data Bus. The Command Bus handles the instruction to the NSE
while the Request Data Bus is the main data path to the NSE.
The 72 bit bi-directional Request Data Bus functions as a multiplexed
address and data bus, which performs the writing and reading of NSE
entries, as well as presenting lookup data to the device.
The NSE Response Bus is comprised of an independent unidirec-
tional Index Bus which drives the result of the lookup (or index) to either
an SRAMdevice or an ASIC. In addition to driving the Index, the NSE
Response Bus also drives the associated SRAMcontrol signals (
CE
/
OE
,
and
WE
) for either ZBT or Synchronous Pipeline Burst SRAMdevices.
A6457drw03
Data
Mask
Features
■
Full Ternary 32K x 72 bit content addressable memory
■
Global Mask Registers
■
40/72/144/288 multiple width lookups
■
200Msustained lookups per second at 72 and 144 width lookups
■
Dual bus interface
■
Cascadable to 8 devices with no glue logic or latency penalty
■
Glueless interface to standard ZBT or
Synchronous Pipelined Burst SRAMs
■
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
■
1.5V match power supply
■
2.5V core and I/O power supply
Command Bus
The Command Bus loads the specific instructions into the NSE. These
include:
■
Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, register or external SRAM.
■
SRAMNo Wait Read
An SRAMNo Wait Read is a Read instruction to an external SRAMthat
can be pipelined within a series of operations and does not require the user
to wait for the Read to complete before loading the next instruction.
■
Lookup
A lookup can be requested in 40-bit, 72-bit, 144-bit or 288-bit widths.
■
SMDL Lookup
The three SMDL Lookup instructions offer the ability to simultaneously
search in mutually exclusive databases which increases the search rate
up to 200 MSPS.
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