參數(shù)資料
型號(hào): 7640
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述: 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù): 5/97頁(yè)
文件大?。?/td> 1885K
代理商: 7640
4
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NAME
I/O
DESCRIPTION
PIN #
P7
3
/IBF
1
/HLDA
P7
4
/OBF
1
I/O
I/O
CMOS I/O port or IBF
1
output to master CPU for data bus buffer 1, or HLDA pin.
IBF
1
and HLDA are mutually exclusive. IBF
1
has priority over HLDA
CMOS I/O port or OBF
1
output to master CPU for data bus buffer 1.
CMOS I/O port or UART2 pin UTXD2 or SIO pin SRDY. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART2 pin URXD2 or SIO pin SCLK. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART2 pin CTS2 or SIO pin SRXD. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART2 pin RTS2 or SIO pin STXD. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
CMOS I/O port or UART1 pin UTXD1.
66
65
P8
0
/UTXD2/SRDY
I/O
32
P8
1
/URXD2/SCLK
I/O
31
P8
2
/CTS2/SRXD
I/O
30
P8
3
/RTS2/STXD
P8
4
/UTXD1
P8
5
/URXD1
P8
6
/CTS1
P8
7
/RTS1
AVcc, AVss
I/O
I/O
29
28
I/O
CMOS I/O port or UART1 pin URXD1.
27
I/O
CMOS I/O port or UART1 pin CTS1.
26
I/O
CMOS I/O port or UART1 pin RTS1.
25
I
Power supply inputs for analog circuitry AVcc = 4.15~ 5.25V, AVss = 0V
Controls the processor mode of the chip. Normally connected to Vss or Vcc.
When the MCU is in EPROM program mode, this pin supplies the programming
voltage to the EPROM.
17,19
CNVss/Vpp
I
9
Vcc,Vss
I
Power supply inputs: Vcc = 4.15~ 5.25V, Vss = 0V
16/74
13/73
RESET
I
To enter the reset state, this pin must be kept 'L' for more that 2
μ
s (20
Φ
cycles
under normal Vcc conditions). If the crystal or ceramic resonator requires more
time to stabilize, extend this 'L' level time appropriately.
An external ceramic or quartz crystal oscillator can be connected between the
XCin and XCout pins. If an external clock source is used, connect the clock
source to the XCin pin and leave the XCout pin open.
Input and output signals to and from the internal clock generation circuit.
Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set
the oscillation frequency. If an external clock is used, connect the clock source
to the Xin pin and leave the Xout pin open.
Loop filter for the frequency synthesizer.
10
XCin
I
12
XCout
O
11
Xin
Xout
I
14
15
O
LPF
O
18
Ext. Cap
I
An external capacitor (Ext. Cap) pin. When the USB transceiver voltage
converter is used, a 2
μ
f or larger capacitor should connect between this pin and
Vss to ensure proper operation of the USB line driver. The voltage converter is
enabled by setting bit 4 of the USB control register (0013
16
) to a
1
.
72
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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