![](http://datasheet.mmic.net.cn/230000/7721_datasheet_15568108/7721_13.png)
7721 Group User’s Manual
vi
Table of contents
13.3 Control............................................................................................................................... 13-19
13.3.1 DMA enabling........................................................................................................... 13-19
13.3.2 DMA requests .......................................................................................................... 13-20
13.3.3 Channel priority levels ............................................................................................ 13-21
13.3.4 Processing from DMA request until DMA transfer execution ............................13-23
13.3.5 Termination of DMA transfer.................................................................................. 13-25
13.3.6 DMA transfer restart after termination ..................................................................13-28
13.4 Operation .......................................................................................................................... 13-30
13.4.1 2-bus cycle transfer................................................................................................. 13-30
[Precautions for 2-bus cycle transfer] ............................................................................... 13-37
13.4.2 1-bus cycle transfer................................................................................................. 13-38
[Precautions for 1-bus cycle transfer] ............................................................................... 13-47
13.4.3 Burst transfer mode................................................................................................. 13-48
[Precautions for burst transfer mode] ............................................................................... 13-50
13.4.4 Cycle-steal transfer mode....................................................................................... 13-51
[Precautions for cycle-steal transfer mode]......................................................................13-52
13.5 Single transfer mode...................................................................................................... 13-54
13.5.1 Setting of single transfer mode ............................................................................. 13-56
13.5.2 Operation in single transfer mode......................................................................... 13-59
13.6 Repeat transfer mode .................................................................................................... 13-61
13.6.1 Setting of repeat transfer mode ............................................................................ 13-63
13.6.2 Operation in repeat transfer mode ........................................................................13-66
13.7 Array chain transfer mode............................................................................................ 13-68
13.7.1 Transfer parameter memory in array chain transfer mode ................................13-70
13.7.2 Setting of array chain transfer mode ....................................................................13-72
13.7.3 Operation in array chain transfer mode ...............................................................13-75
[Precautions for array chain transfer mode] ....................................................................13-79
13.8 Link array chain transfer mode................................................................................... 13-80
13.8.1 Transfer parameter memory in link array chain transfer mode.........................13-82
13.8.2 Setting of link array chain transfer mode.............................................................13-84
13.8.3 Operation in link array chain transfer mode ........................................................13-87
[Precautions for link array chain transfer mode] .............................................................13-97
13.9 DMA transfer time........................................................................................................... 13-98
13.9.1 Cycle-steal transfer mode....................................................................................... 13-98
13.9.2 Burst transfer mode............................................................................................... 13-101
CHAPTER 14 DRAM CONTROLLER
14.1 Overview ............................................................................................................................. 14-2
14.2 Block description.............................................................................................................. 14-2
14.2.1 DRAM control register............................................................................................... 14-3
14.2.2 Refresh timer.............................................................................................................. 14-5
14.2.3 Address comparator .................................................................................................. 14-6
14.2.4 RAS and CAS generating circuit ............................................................................. 14-6
14.2.5 Address multiplexer ................................................................................................... 14-6
14.3 Setting for DRAMC ........................................................................................................... 14-7
14.4 DRAMC operation ............................................................................................................. 14-8
14.4.1 Waveform example of DRAM control signals ........................................................14-8
14.4.2 Refresh request ....................................................................................................... 14-10
14.5 Precautions for DRAMC ................................................................................................ 14-12