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參數(shù)資料
| 型號： | 78P2352-IELR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 39/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SDH SONET 2CH 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 6 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
Plesiochronous Tx Serial Mode
Figure 3 represents a common condition where a
serial transmit clock is not available and/or the data
is not source synchronous to the reference clock
input.
In this mode, the 78P2352 will recover a
transmit clock from the serial plesiochronous data
and bypass the internal FIFO and re-timing block.
This mode is commonly used for mezzanine cards,
modules, and any application where the reference
clock cannot always be synchronous to the transmit
source clock/data.
TDK
78P2352
Framer/
Mapper
NRZ
140 / 155 MHz
Reference
Clock
SOxDP/N
SOxCKP/N
SIxDP/N
CKREFP
RXxP/N
CMIxP/N
XFMR
CMI
Coax
XO
Figure 3: Plesiochronous; data only
(Tx CDR enabled, FIFO bypassed)
Synchronous Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4
÷ 4) or
38.88MHz (STM1
÷ 4) synchronous clock. These
inputs are re-timed in a 4x8 clock decoupling FIFO
and then to a serializer for transmission. Because
the data is passed through the FIFO and re-timed
using a synthesized clock, the transmit nibble clock
and data for both channels must be source
synchronous to the provided reference clock.
For maximum compatibility with legacy ASICs, the
78P2352 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively.
Note: A loop-timing mode is also available to
allow external remote loopbacks (i.e. line
loopback in framer). In this mode, the FIFO is
still enabled, but the transmit data will be re-
timed using the recovered receive clock
HW Control Pins
SW Control Bits
Parallel
Mode
SDI_PAR
CKMODE
PAR
PMODE
Slave
High
Low
1
0
Slave +
*Loop-timing
High
Float
1
0
Master
High
1
*To
enable
Loop-timing
in
software
mode
set
SMOD[1:0]=11
4-bit CMOS TTL
TDK
78P2352
Framer/
Mapper
Reference
Clock
CKREFP/N
RXxP/N
CMIxP/N
XFMR
CMI
Coax
POx[3:0]D
POxCK
PIxCK
PIx[3:0]D
34/39 MHz
Figure 4: Slave Parallel Mode
4-bit CMOS TTL
TDK
78P2352
Framer/
Mapper
Reference
Clock
CKREFP/N
RXxP/N
CMIxP/N
XFMR
CMI
Coax
POx[3:0]D
POxCK
PTOxCK
PIx[3:0]D
34/39 MHz
Figure 5: Master Parallel Mode
Transmit FIFO Description
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error.
If the clock wander exceeds the
specified limits, the FIFO will over or under flow, and
the FERRx register signal will be asserted. This
signal can be used to trigger an interrupt.
This
interrupt event is automatically cleared when a FIFO
Reset (FRSTx) pulse is applied, and the FIFO is re-
centered.
Notes:
1) External remote loopbacks (i.e. loopback
within
framer)
are
not
possible
in
synchronous
operation
(FIFO
enabled)
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2352 is configured for loop-timing.
2) Most E4 applications will not allow the use of
the dual channel 78P2352 as each channel
is asynchronous to each other.
Teridian
recommends using the single channel
78P2351 if one cannot control the E4 timing
reference for each channel.
3) During IC power-up or transmit power-up,
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow. As such, the FIFO should be
manually reset using FRST anytime the
transmitter is powered-up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78P2352-IGT | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Dual Channel OC-3/ STM1-E/ E4 LIU |
| 78P2352-IGT/F | 功能描述:接口 - 專用 Dual Ch OC-3/STM1-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2352-IGTR | 功能描述:接口 - 專用 Dual Ch OC-3/STM1-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2352-IGTR/F | 功能描述:接口 - 專用 Dual Ch OC-3/STM1-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P236-IP | 制造商:SSI 功能描述: |
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