參數(shù)資料
型號: 79RC32T355-133DH
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: IDT Interprise Integrated Communications Processor
中文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MO-143FA-1, QFP-208
文件頁數(shù): 32/47頁
文件大?。?/td> 987K
代理商: 79RC32T355-133DH
32 of 47
May 25, 2004
IDT 79RC32355
Signal
Symbol
Reference
Edge
133MHz
150MHz
180MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
USB
USBCLKP
1
Tperiod1
none
19.79
21.87
19.79
21.87
19.79
21.87
ns
Figure 17
Thigh1,Tlow1
8.3
8.3
8.3
ns
Trise1,Tfall1
3
3
3
ns
Tjitter1
0.8
0.8
0.8
ns
1/4th of the mini-
mum Source data
jitter
USBDN, USBDP
Trise2
4
20
4
20
4
20
ns
Universal Serial Bus
Specification
(USBS) Revision
1.1: Figures 7.6 and
7.7.
Tfall2
4
20
4
20
4
20
ns
USBS Revision 1.1:
Figures 7.6 and 7.7.
USBDN and USBDP
Rise and Fall Time
Matching
90
111.11
90
111.11
90
111.11
%
USBS Revision 1.1:
Note 10, Section
7.1.2.
Data valid period
Tstate
60
60
60
ns
Skew between USBDN
and USBDP
0.4
0.4
0.4
ns
USBS Revision 1.1:
Section 7.1.3
Source data jitter
3.5
3.5
3.5
ns
USBS Revision 1.1:
Table 7-6
Receive data jitter
12
12
12
ns
Source EOP length
Tseop
160
175
160
175
160
175
ns
Receive EOP length
Treop
82
82
82
ns
EOP jitter
-2
5
-2
5
-2
5
ns
Full-speed Data Rate
Tfdrate
11.97
12.03
11.97
12.03
11.97
12.03
MHz
Average bit rate,
USBS Section
7.1.11.
Frame Interval
0.9995 1.0005 0.9995 1.0005 0.9995 1.0005
ms
USBS Section
7.1.12.
Consecutive Frame
Interval Jitter
42
42
42
ns
Without frame
adjustment.
126
126
126
ns
With frame adjust-
ment.
1
USB clock (USBCLKP) frequency must be less than CLKP frequency.
Table 11 USB AC Timing Characteristics
相關PDF資料
PDF描述
79RC32T355-133DHI IDT Interprise Integrated Communications Processor
79RC32T355-150DH IDT Interprise Integrated Communications Processor
79RC32T355-150DHI IDT Interprise Integrated Communications Processor
79RC32T355-180DH IDT Interprise Integrated Communications Processor
79RC32T355-180DHI IDT Interprise Integrated Communications Processor
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