IDT PCI Bus Interface
PCI Satellite Mode
79RC32438 User Reference Manual
10 - 15
November 4, 2002
Notes
The internal arbiter supports up to six external devices. The default arbitration algorithm used by the
internal arbiter is selected by the PCI mode during boot configuration. The algorithm may be modified
through the Arbiter Arbitration Algorithm (AAA) bit in the PCIC register. The two algorithms are:
Round robin arbitration algorithm - ownership is granted in a fixed rotating sequence (RC32438,
PCIREQN[0], PCIREQN[1], PCIREQN[2], PCIREQN[3], PCIREQN[4], PCIREQN[5]).
Fixed priority arbitration algorithm - the priority order (highest to lowest) is RC32438, PCIREQN[0],
PCIREQN[1], PCIREQN[2], PCIREQN[3], PCIREQN[4], PCIREQN[5].
The RC32438 internal arbiter will guarantee that the PCI “Trhff” (time from reset high-to-first-frame#
assertion) specification will be met by not granting the bus for at least eight clock cycles after negation of
the PCI reset or the enabling of the PCI interface.
Interrupts
In host mode, the RC32438 does not provide any dedicated interrupt inputs. GPIO pins may be used as
interrupt inputs. Although no GPIO pins are dedicated for PCI interrupts, GPIO pins GPIO[29:26] have PCI
buffers (refer to Table 1.3 in Chapter 1).
The PCI messaging unit operates in both satellite and host modes. The PCI messaging unit interrupt
output (i.e., PCIMUINTN) is a GPIO alternate function output (refer to Table 12.1 in Chapter 12). When
configured as an alternate function, this pin is tri-stated when not asserted (i.e., it acts as an open collector
output).
PCI Satellite Mode
Reset and Initialization
In PCI satellite mode, the PCI reset pin (PCIRSTN) is an input. Assertion of the PCI reset pin causes the
RC32438 to perform a warm reset and to reset the state of all registers in the PCI interface to their initial
value (including PCI configuration registers).
The PCI bus interface supports two PCI satellite operating modes. The two satellite operating modes
are: PCI satellite mode with target not ready, and PCI satellite mode with suspended CPU execution. The
operating mode is selected by the PCI mode field during boot configuration.
Pin Name
Type
Description
PCIREQN[5:0]
I
PCI Request
. The assertion of these signals indicates to the internal
RC32438 arbiter that an agent desires use of the PCI bus.
PCIGNTN[5:0]
O
PCI Grant
. The assertion of these signals indicates to the agent that the
internal RC32438 arbiter has granted the agent access to the PCI bus.
Table 10.3 PCI Arbitration Pin Functionality in PCI Host Mode with Internal Arbiter Enabled
Pin Name
Type
Description
PCIREQN[0]
O
PCI Request
. This signal is asserted by the RC32438 to request use of
the PCI bus. While PCIRSTN is asserted, the RC32438 tri-states this
signal.
PCIREQN[5:1]
O
Unused
. These signals are unused in this mode and driven high.
PCIGNTN[0]
I
PCI Grant
. This signal is asserted by an external arbiter to indicate to
the RC32438 that access to the PCI bus has been granted. While PCIR-
STN is asserted, the RC32438 ignores the state of this signal.
PCIGNTN[5:1]
O
Unused
. These signals are unused in this mode and driven high.
Table 10.4 PCI Arbitration Pin Functionality in PCI Host Mode Using External Arbiter