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IDT DMA Controller
Data Flow within the RC32438
79RC32438 User Reference Manual
9 - 4
November 4, 2002
Notes
speed requirements of the interface. However, for fast interfaces like Ethernet, using the core to transfer the
data is not recommended. Rather, the associated DMA channels should be used to maintain the wire speed
of these interfaces.
DMA Controller
As mentioned above, a DMA channel should be used with a fast peripheral to maintain the wire speed
on the interface. The DMA Controller plays a critical role in the data movement within the RC32438 and in
maintaining the wire speed on the various interfaces. The DMA Controller is one of the most complex
blocks on the RC32438 and offers a number of capabilities tailored to enhance data movement capabilities.
Understanding the operation of the DMA Controller is critical to understanding the operation and the data
movement within the RC32438. The DMA Controller is tightly coupled to the internal IPBus and to the
various on chip peripherals to enable the RC32438 to meet the wire speed of the various interfaces. Figure
9.1 illustrates a simplified block diagram of the DMA Controller and the internal IPBus on the RC32438.
Figure 9.1 DMA Block Diagram
The DMA Controller supports ten DMA channels. These DMA channels can be grouped into two catego-
ries: dedicated channels and multiplexed channels. Each of the dedicated DMA channels service only one
peripheral in one direction (input or output). As an example, DMA channel 2 services the Ethernet
Controller in the input direction only. The multiplexed DMA channels service more than one peripheral in
both directions.
The DMA Controller implements fly-by DMA operations. A fly-by operation transfers data between an
on-chip peripheral and memory using a single transaction. Non-fly-by operations require two transactions:
One to move data between an on-chip peripheral and an internal buffer
Another to move the data from the internal buffer to memory.
The DMA Controller arbitrates for the IPBus and then monitors the fly-by transfer of data between the
Memory Controller and the on-chip peripheral.
The fly-by implementation enhances the bandwidth of the DMA because it eliminates the extra clock
cycles that would be needed to temporarily store the data.
The DMA Controller supports any length of packet transfer. Each packet is divided into bursts of up to 16
words maximum. Some interfaces can generate smaller bursts. The DMA Controller re-arbitrates for the
tain a balance between the DMA transfers and the 4Kc core instruction fetches and data transfers.
No Alignment Restrictions
To support the needs of most data communication protocols and standard data communication drivers,
the DMA Controller does not impose any alignment restrictions on the data. The data in memory to be
transferred by the DMA Controller can be located anywhere in the main memory and start on any byte
boundary. For example, the data to be transferred can start at byte 2 within a word and be 1000 bytes long.
DMA
State Machine
IPBus
Channel 0
Channel 9
DDR
Controller
DDR
On-chip
peripherals
Device
Controller
Other
Memory
RC32438
External Systems
PMBus