參數(shù)資料
型號(hào): 7C33128PFS36A
英文描述: 3.3V 128K x 32/36 pipeline burst synchronous SRAM
中文描述: 3.3 128K的x 32/36管道爆裂同步SRAM
文件頁數(shù): 10/11頁
文件大?。?/td> 231K
代理商: 7C33128PFS36A
7C33128PFS32A
7C33128PFS36A
2/1/01
Alliance Semiconductor
P. 10 of 11
AC test conditions
Output load: see Figure B, except for t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C.
Notes
1
2
3
4
5
6
For test conditions, see
AC Test Conditions
, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE
is less than t
LZOE
; and t
HZC
is less than t
LZC
at any given temperature and voltage.
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to
GWE
,
BWE
,
BW[a:d].
Chip select refers to
CE0
,
CE1
,
CE2
.
7
8
351
5 pF*
317
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Input pulse level: GND to 3V See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
Package Dimensions
100-pin quad flat pack (TQFP)
Dimensions in millimeters
TQFP
Min
0.05
1.35
0.22
0.09
13.90
19.90
0.65 nominal
15.90
21.90
0.45
1.00 nominal
Max
0.15
1.45
0.38
0.20
14.10
20.10
A1
A2
b
c
D
E
e
Hd
He
L
L1
α
16.10
22.10
0.75
He
E
Hd
D
b
e
A1 A2
L1
L
c
α
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