參數(shù)資料
型號: 7LVC374APWDH
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State
中文描述: LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
文件頁數(shù): 7/12頁
文件大?。?/td> 101K
代理商: 7LVC374APWDH
Philips Semiconductors
Product specification
74LVC374A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
1998 Jul 29
7
AC WAVEFORMS
V
M
= 1.5V at V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V; V
X
= V
OL
+ 0.1 V
CC
at V
CC
V
Y
= V
OH
–0.3V at V
CC
2.7V; V
Y
= V
OH
– 0.1 V
CC
at V
CC
2.7V; V
= 0.5 V
at V
2.7V.
2.7V
2.7V
t
w
t
PLH
CP INPUT
Qn OUTPUT
V
M
V
M
V
M
V
M
V
M
V
I
GND
V
OH
V
OL
SA00394
t
PHL
1/f
max
Waveform 1. Clock (CP) to output (Q
n
) propagation delays, the
clock pulse width, output transition times and the maximum
clock pulse frequency.
V
M
SW00107
V
I
GND
éééé
V
OH
ééééééé
ééééééé
ééééééé
V
M
Dn
INPUT
V
I
GND
V
M
Qn
OUTPUT
V
OL
CP
INPUT
t
su
t
h
t
su
t
h
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 2. Data setup and hold times for the D
n
input to the
CP input.
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
Q
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
Q
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00207
Waveform 3. 3-State enable and disable times.
TEST CIRCUIT
PULSE
GENERATOR
V
I
R
T
D.U.T.
V
O
C
L
50pF
S
1
2 x V
CC
Open
GND
500
500
V
CC
V
I
2.7V
V
CC
2.7V
2.7V – 3.6V
Test
S
1
GND
t
PLZ
/t
PZL
t
PHZ
/t
PZH
2 x V
CC
t
PLH
/t
PHL
Open
SY00003
V
CC
Waveform 4. Load circuitry for switching times.
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