參數(shù)資料
型號(hào)： 80930AD
廠商： Intel Corp.
英文描述： Universal Serial Bus Microcontroller(通用串行總線微控制器)
中文描述： 通用串行總線控制器（通用串行總線微控制器）
文件頁(yè)數(shù)： 11/38頁(yè)
文件大?。?/td> 226K
代理商： 80930AD
ADVANCE INFORMATION
7
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
3.0
SIGNALS
Table 5. Signal Descriptions
Signal
Name
Type
Description
Alternate Function
A17
O
18th Address Bit (A17).
Output to memory as 18th exter-
nal address bit (A17) in extended bus applications, depend-
ing on the values of bits RD0 and RD1 in configuration byte
UCONFIG0. See also RD#, PSEN#.
P1.7/CEX4/WCLK
A16
A15:8
AD7:0
O
Address Line 16
.
See RD#.
RD#
O
Address Lines
. Upper address lines for the external bus.
P2.7:0
I/O
Address/Data Lines
. Multiplexed lower address lines and
data lines for external memory.
P0.7:0
ALE
O
Address Latch Enable (ALE)
. ALE signals the start of an
external bus cycle and indicates that valid address informa-
tion is available on lines A15:8 and AD7:0. An external latch
can use ALE to demultiplex the address from the
address/data bus.
PROG#
AV
CC
PWR
Analog V
CC
. A separate V
CC
input for the phase-locked loop
circuitry.
CEX2:0
CEX3
CEX4
I/O
Programmable Counter Array (PCA) Input/Output Pins
.
These are input signals for the PCA capture mode and out-
put signals for the PCA compare mode and PCA PWM
mode.
P1.5:3
P1.6/WAIT#
P1.7/A17/WCLK
D
M
0
D
P
0
EA#
I/O
Data Minus
. USB minus data line interface.
—
I/O
Data Plus
. USB plus data line interface.
—
I
External Access
. Directs program memory accesses to
on-chip or off-chip code memory. For EA# strapped to
ground, all program memory accesses are off-chip. For EA#
strapped to V
, program accesses on-chip ROM if the
address is within the range of the on-chip ROM; otherwise,
the access is off-chip. The value of EA# is latched at reset.
For devices without on-chip ROM, EA# must be strapped to
ground.
ECAP
I
External Capacitor
. Must be connected to a 1 μF capacitor
(or larger) to ensure proper operation of the differential line
driver. The other lead of the capacitor must be connected to
V
SS
.
PCA External Clock Input
. External clock input to the 16-
bit PCA timer.
ECI
I
P1.2
INT1:0#
I
External Interrupts 0 and 1
. These inputs set bits IE1:0 in
the TCON register. If bits IT1:0 in the TCON register are
set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If
bits INT1:0 are clear, bits IE1:0 are set by a low level on
INT1:0#.
P3.3:2
P0.7:0
I/O
Port 0
. This is an 8-bit, open-drain, bidirectional I/O port.
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
AD7:0
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