![](http://datasheet.mmic.net.cn/340000/80930AD_datasheet_16452116/80930AD_36.png)
32
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode
Symbol
Parameter
8x930Ax3/8x930Ax4
Compatibility Mode (ns)
(EDF# =1) (1)
T
AVLL
T
LLAX
T
WLWH
T
LLRL
T
LHAX
T
RLDV
T
RLAZ
T
RHDZ
2
T
RHLH
2
T
WHLH
T
AVDV
2
T
AVRL
T
AVWL
1
NOTES:
1.
2.
Address Valid to ALE Low
(0.5+M)T
CLK
- 13 [min]
10 [min]
Address Hold after ALE Low
WR# Pulse Width
(1+N)T
CLK
- 10 [min]
10 [min]
ALE Low to RD# or PSEN# low
ALE High to Address Hold
(1+M)T
CLK
- 27 [min]
(1+N)T
CLK
- 30 [max]
3 max (2)
RD# or PSEN# Low to Valid Data/Inst. In
RD# or PSEN# Low to Address Float
Data Float After PSEN# or RD# High
T
CLK
+ 10 [max]
T
CLK
+ 10 [min]
T
CLK
+10 [min]
(2+M+N)T
CLK
- 38 [max]
(1+M)T
CLK
- 40 [min]
(1+M)T
CLK
- 40 [min]
RD# or PSEN# High to ALE High (data)
WR# High to ALE High
Address (demux’ed) Valid to Valid Data/Instr. In
Address Valid to RD# or PSEN# Low
Address (mux’ed) Valid to WR# Low
Device configured with default data float timing for fast memory interface.
Typical value is 0 ns.
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings
Sym-
bol
Parameter
Default Data Float
Timing (ns)
Compatibility Mode
(EDF# =1) (1,2,4,5)
Extended Data Float
Timing (ns)
Increased T
mode
(EDF#=0) (1,3,4,5)
T
LLAX
T
RLRH
T
WLWH
T
LLRL
T
LHAX
T
RLDV
T
RHDZ
1
NOTES:
1.
2.
3.
4.
5.
Address Hold after ALE Low
10 [min]
20 [min]
RD# or PSEN# Pulse Width
(1+N)T
CLK
- 10 [min]
(1+N)T
CLK
- 10 [min]
10 [min]
(1+N)T
CLK
- 32 [min]
(1+N)T
CLK
- 32 [min]
20 [min]
WR# Pulse Width
ALE Low to RD# or PSEN# low
ALE High to Address Hold
(1+M)T
CLK
- 27 [min]
(1+N)T
CLK
- 30 [max]
10 [max]
(0.5+M)T
CLK
+ 15 [min]
(1+N)T
CLK
- 50 [max]
(0.5)T
CLK
- 5 [max]
RD# or PSEN# Low to Valid Data/Inst. In
Instruct. Float After PSEN# or RD# High
Worst-case numbers based on silicon data collected to date.
Device configured with default data float timing for fast memory interface.
Device configured with extended data float timing for slow memory interface.
The values listed are for 12 MHz. For 6 MHz, the value of T
will double and will equal 166.6 ns.
M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.