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參數(shù)資料
| 型號(hào)： | 80931AA |
| 廠商： | Intel Corp. |
| 英文描述： | Universal Serial Bus Peripheral Controller(通用串行總線HUB外設(shè)微控制器) |
| 中文描述： | 通用串行總線外設(shè)控制器（通用串行總線集線器外設(shè)微控制器） |
| 文件頁數(shù)： | 18/26頁 |
| 文件大小： | 195K |
| 代理商： | 80931AA |
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8x931AA, 8x931HA USB Peripheral Controller
18
Advance Information Datasheet
5.2
DC Characteristics
Table 14. DC Characteristics at Operating Conditions (Sheet 1 of 2)
Symbol
Parameter
Min
Typical
(1)
Max
Units
Test Conditions
V
IL
Input Low Voltage
(except EA#)
–0.5
0.2 V
CC
– 0.1
V
V
IL
1
Input Low Voltage
(EA#)
0
0.2 V
CC
– 0.3
V
V
IH
Input High Voltage
(except XTAL1, RST)
0.2 V
CC
+ 0.9
V
CC
+ 0.5
V
V
IH
1
Input High Voltage
(XTAL1, RST)
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
(port 1, 2, 3)
(2)
0.3
0.45
1.0
V
I
OL
= 100 μA
I
OL
= 1.6 mA
I
OL
= 3.5 mA
V
OL
1
Output Low Voltage
(port 0, ALE, PSEN#,
SOF#)
(2)
0.3
0.45
1.0
V
I
OL
= 200 μA
I
OL
= 3.2 mA
I
OL
= 7.0 mA
V
OL
2
Output Low Voltage
(LED 0, 1, 2, 3)
2.0
3.0
V
I
OL
= 6 mA
I
OL
= 22 mA
V
OH
Output High Voltage
(port 1, 2, 3, ALE,
PSEN#, SOF#)
(3)
V
CC
– 0.3
V
CC
– 0.7
V
CC
– 1.5
V
I
OH
= –10 μA
I
OH
= –30 μA
I
OH
= –60 μA
V
OH
1
Output High Voltage
(port 0 in external
address space)
(3)
V
CC
– 0.3
V
CC
– 0.7
V
CC
– 1.5
V
I
OH
= –200 μA
I
OH
= –3.2 mA
I
OH
= –7.0 mA
I
IL
Logical 0 Input
Current
(port 1,2,3)
–50
μA
V
IN
= 0.45 V
I
LI
Input Leakage Current
(port 0)
±
10
μA
V
IN
= V
IL
or V
IH
I
TL
Logical 1-to-0
Transition Current
(Port 1, 2,3)
–650
μA
V
IN
= 2.0 V
R
RST
RST Pulldown
Resistor
40
100
K
C
IO
Pin Capacitance
10
pF
F
OSC
= 12 MHz
T
A
= 25°C
NOTES:
1. Typical values are obtained using V
= 5.0V, T
= 25°C and are not guaranteed.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE
or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the V
on ALE and PSEN to drop below the V
CC
specification when the address lines are stabilizing.
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