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參數(shù)資料
| 型號： | 80931AA |
| 廠商： | Intel Corp. |
| 英文描述： | Universal Serial Bus Peripheral Controller(通用串行總線HUB外設(shè)微控制器) |
| 中文描述： | 通用串行總線外設(shè)控制器（通用串行總線集線器外設(shè)微控制器） |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 195K |
| 代理商： | 80931AA |
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8x931AA, 8x931HA USB Peripheral Controller
Advance Information Datasheet
19
5.3
Explanation of Timing Symbols
Table defines the timing symbols used in Tables 14 through and the associated timing diagrams.
They have the form Txxyy, where the character pairs represent a signal and its condition. Timing
symbols represent the time between two signal / condition points.
I
PD
Powerdown Current
USB suspend
145
175
μA
I
DL
Idle Mode I
CC
40
mA
F
CLK
=6 MHz
30
F
CLK
=3 MHz
I
CC
Active I
CC
70
mA
F
CLK
= 6 MHz
50
F
CLK
= 3MHz
U
ZDRV
USB Drivers Output
10
25
K
Table 14. DC Characteristics at Operating Conditions (Sheet 2 of 2)
Symbol
Parameter
Min
Typical
(1)
Max
Units
Test Conditions
NOTES:
1. Typical values are obtained using V
= 5.0V, T
= 25°C and are not guaranteed.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE
or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the V
on ALE and PSEN to drop below the V
CC
specification when the address lines are stabilizing.
Table 15. AC Timing Symbol Definitions
Symbol
Definition
A
Address: A15:8, A7:0
C
External Clock (XTAL1)
D
Data In: D7:0
L
ALE: Address Latch Enable
P
Program Store Enable (PSEN#)
Q
Data Out: D7:0
R
Read: RD#
W
Write: WR#
Character
Condition
H
High
L
Low
V
Valid, Setup
X
No Longer Valid, Hold
Z
Floating (low impedance)
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