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參數(shù)資料
| 型號： | 80960KB |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded 32-Bit Microprocessor With Integrated Floating-Point Unit(帶有集成的浮點單元的嵌入式32位微處理器) |
| 中文描述： | 嵌入式32位微處理器集成浮點單元（帶有集成的浮點單元的嵌入式32位微處理器） |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 58K |
| 代理商： | 80960KB |
Upgrading System Designs from i960
Kx to the i960 Jx Processors
Technical Note
5
CACHE
BADAC#
2.3
Bus Arbitration
The HOLD/HOLDA protocol is enhanced so that the 80960Jx processor cannot pass directly from
a T
d
bus state to the T
h
(HOLD) bus state without passing through the T
r
state(s). This change is
necessary to support the RDYRCV# pin described previously. Another difference is that 80960Jx
processors respond to HOLD requests during reset (80960Kx processors cannot). The timing
relationship of the HOLD and HOLDA pins is unchanged.
The 80960Kx processor has an open-drain LOCK#. The processor tests the state of this pin prior to
asserting it. The 80960Jx processors have a one-way LOCK# output pin, implemented in three-
state logic.
2.4
Interrupt Control Inputs
The 80960Jx processor’s interrupt control unit is identical to that of the i960 CA/CF processors. It
has eight general purpose XINT# interrupt pins and one NMI# pin. Note that these are active-low
inputs, but, unlike the i960 CA/CF device, the pins are sampled on the rising clock edge. For future
compatibility, avoid using the 80960KA/KB processor’s Interrupt/Interrupt Acknowledge protocol,
as this model is not supported in the i960 Jx microprocessor family.
The 80960Jx processors do not support Inter-Agent Communication (IAC messaging), so there is
no IAC# input pin.
2.5
Other Hardware Compatibility Notes
The active sense of the reset signal changed on the 80960Jx processors from high to low.
On the 80960Jx processor, the LOCK# pin is tested upon RESET# de-assertion. If it is low, the
processor enters the ONCE three-state test mode. The 80960Kx processor does not support ONCE
mode.
All versions of the 80960Jx processor are clocked at the bus frequency, even if the core clock is
doubled or tripled (80960JD or 80960JT respectfully). The 80960Kx processor is clocked at 2
x
the
bus frequency.
3.0
Software Considerations
3.1
IBR-Initialization Boot Record
The location of the Initialization Boot Record is different on the 80960Jx and the 80960Kx. The
IBR on the 80960Kx is located at 0x00000000, whereas the IBR for the 80960Jx is at
0xFEFFFF30. On the 80960Jx, the area where the 80960Kx IBR is located is in internal data RAM.
However on the 80960Kx the area where the 80960Jx boot code is located is reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80960MC | Embedded 32Bit Microprocessor With Integrated Floating_Point Unit And Memory Unit(帶有集成的浮點單元和存儲器管理單元的嵌入式32位微處理器) |
| 80960RM | 80960RM I/O Processor(80960RM I/O 處理器) |
| 80960RN | 80960RN I/O Processor(80960RN I/O 處理器) |
| 80960SA | Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器) |
| 80960SB | Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80960MC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT |
| 80960SA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS |
| 80960SB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS |
| 80961-01 | 制造商:Glenair 功能描述:EARTH BOND M10 FOR AL 4MM T |
| 809621-000 | 制造商:TE Connectivity 功能描述:809621-000 |
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