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參數(shù)資料
| 型號： | 80960KB |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded 32-Bit Microprocessor With Integrated Floating-Point Unit(帶有集成的浮點(diǎn)單元的嵌入式32位微處理器) |
| 中文描述： | 嵌入式32位微處理器集成浮點(diǎn)單元（帶有集成的浮點(diǎn)單元的嵌入式32位微處理器） |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 58K |
| 代理商： | 80960KB |
Upgrading System Designs from i960
Kx to the i960 Jx Processors
Technical Note
7
does not use resumption records. (Resumption records are used on the 80960Kx for long
floating-point instructions.)
The internal state bits in the Process Controls register are unimplemented on the 80960Jx. The
user should not write to these bits on either the 80960Kx or the 80960Jx.
The 80960Jx does not have a stopped state.
Register bypassing is implemented on the 80960Jx, and is not on the 80960Kx. The following
is an example of register bypassing:
mov r6, fp The FP is written out on this step.
addo fp, 0, 55
This instruction does not read in the FP, but uses its value from the previous instruction. The actual
FP could differ from the FP used in the addo instruction due to the fact that the processor ignores
the lower 4 bits of the actual FP.
3.6
Interrupts
The 80960Jx uses the interrupt controller from the CX, which is different from the 80960Kx. For
complete details of these processor’s interrupt controllers, refer to their respective user’s manuals.
3.7
Memory Control
While the 80960Kx has no built-in memory control, the 80960Jx has 8 programmable memory
regions. It contains 8 PMCON registers for programming bus width for the physical memory
regions. It also uses 2 types of logical templates each comprised of 2 logical memory control
registers (LMMRs and LMADRs) to control data cache enabling for its specific region. The
80960Jx has a default logical memory configuration register (DLMCON) for accesses that do not
fall inside one of the two logical memory templates. DLMCON also controls byte ordering for the
entire memory map.
3.8
IACs
IAC (inter-agent communication) requests are not implemented on the 80960Jx. The following is a
list of all of the 80960Kx IACs and a description of how their functions can be accomplished on the
80960Jx:
Continue Init IAC is not needed on the 80960Jx.
The functionality of a Freeze IAC can be accomplished on the 80960Jx by putting the
processor into HALT mode.
Software Interrupts are initiated with
sysctl
instruction on the 80960Jx.
The functionality of the Purge Instruction Cache IAC is achieved on the 80960Jx using a
sysctl
or the new
icctl
instruction.
The functionality of the Reinitialize Processor IAC is achieved on the 80960Jx using a
sysctl
.
The Set Breakpoint IAC function is entirely different on the 80960Jx. The same functionality
is accomplished on the 80960Jx by obtaining rights to the breakpoint registers using
sysctl
.
Then, the registers can be written to directly as MMRs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80960MC | Embedded 32Bit Microprocessor With Integrated Floating_Point Unit And Memory Unit(帶有集成的浮點(diǎn)單元和存儲器管理單元的嵌入式32位微處理器) |
| 80960RM | 80960RM I/O Processor(80960RM I/O 處理器) |
| 80960RN | 80960RN I/O Processor(80960RN I/O 處理器) |
| 80960SA | Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器) |
| 80960SB | Embedded 32-Bit Microprocessor With 16-Bit Burst Data Bus(帶有16位脈沖串?dāng)?shù)據(jù)總線的嵌入式 32-BIT微處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80960MC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT |
| 80960SA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS |
| 80960SB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS |
| 80961-01 | 制造商:Glenair 功能描述:EARTH BOND M10 FOR AL 4MM T |
| 809621-000 | 制造商:TE Connectivity 功能描述:809621-000 |
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